Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Supports SoC customers to ensure high-quality integration and verification of the IP block. Drives quality assurance compliance for smooth IP-SoC handoff.
Bachelor’s Degree in electrical/computer engineering or related field and 2+ years of experience Or a master’s degree in electrical/computer engineering or related field. 2+ years of RTL coding and/or IP integration experience into SoC design. Experience in design related tools such as LINT, CDC, PT-STA, Fishtail, Power UPF etc & design concept such as data flow, algorithm state machine, finite state machines, and timing charts. Knowledge on FPGA background would be a plus. Highly motivated individual, team player with good communication skill.
Top Skills
What We Do
Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.
