Responsible to lead, define & implement the design (micro-architecture, RTL, linting, CDC, SDC, UPF/power gating, synthesis) of high speed digital design in next generation IO in cutting edge technology node with multi GigaHz design.
Work closely with verification team for design test plan and validation review and back-end team for floor planning, physical implementation, STA timing closure.
Work on post Silicon debug/characterization support of the designs.
BS/MS or PhD in Electronics Engineering with minimum of 10 years of ASIC frontend experience
Strong in communication, leadership, investigation, problem solving & analytical skill
Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments
Knowledge of Spyglass, Synthesis, STA (PT), UPF, UVM, Spice and DFT.
Knowledge scripting desirable
Top Skills
What We Do
Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.
