Front End ASIC RTL/Logic Senior Design Engineer

Reposted 3 Days Ago
Be an Early Applicant
Penang, Daerah Timor Laut, Penang, MYS
In-Office
10-10 Annually
Expert/Leader
Artificial Intelligence • Internet of Things • Machine Learning
The Role
Lead the design of high-speed digital ASICs, collaborating with verification and back-end teams for implementation, timing closure, and post-silicon support.
Summary Generated by Built In
Job Details:

Job Description:
  • Responsible to lead, define & implement the design (micro-architecture, RTL, linting, CDC, SDC, UPF/power gating, synthesis) of high speed digital design in next generation IO in cutting edge technology node with multi GigaHz design.

  • Work closely with verification team for design test plan and validation review and back-end team for floor planning, physical implementation, STA timing closure.

  • Work on post Silicon debug/characterization support of the designs.

Qualifications:
  • BS/MS or PhD in Electronics Engineering with minimum of 10 years of ASIC frontend experience

  • Strong in communication, leadership, investigation, problem solving & analytical skill

  • Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments

  • Knowledge of Spyglass, Synthesis, STA (PT), UPF, UVM, Spice and DFT.

  • Knowledge scripting desirable

Job Type: Regular

Shift:Shift 1 (Malaysia)

Primary Location:Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Skills Required

  • BS/MS or PhD in Electronics Engineering
  • Minimum of 10 years of ASIC frontend experience
  • Proficiency with RTL coding using HDL language(s)
  • Knowledge of Spyglass, Synthesis, STA (PT), UPF, UVM, Spice and DFT
  • Knowledge scripting desirable

Altera (altera.com) Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Altera (altera.com) and has not been reviewed or approved by Altera (altera.com).

  • Retirement Support Feedback suggests retirement programs are robust, with offerings such as a 401(k) and a pension. This breadth supports long-term financial security.
  • Leave & Time Off Breadth Feedback suggests time-off policies are generous, including PTO, paid sick days, and paid holidays. Wellness initiatives like gym memberships further support balance.
  • Parental & Family Support Feedback suggests parental leave is generous. Family-building support, including fertility benefits and adoption reimbursement, is highlighted as part of the package.

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The Company
HQ: San Jose, California
1,612 Employees
Year Founded: 1983

What We Do

Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.

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