Jobs at Altera (altera.com)

Develop and lead Altera’s embedded processing product narrative, positioning FPGA-based solutions across software stacks, processors, peripherals, and RTOS/OS ecosystems. Create customer-facing technical content, sales enablement assets, competitive messaging, and vertical-specific strategies. Translate complex embedded architectures and technologies, including HPS and Nios V RISC-V processors, into clear customer value and business outcomes while identifying market trends and supporting go-to-market campaigns.

Participate in FPGA high-speed protocol IP development, including product specification, RTL design and coding, verification, simulation, emulation prototyping, software tool development, IP integration, and hardware validation. The structured graduate program provides hands-on experience with FPGA architecture, development flows, and real-world projects while working with experienced engineers.

Design and develop FPGA circuits and IPs, including core fabric logic, interconnects, clocking, memory, and network-on-chip components. Perform microarchitecture, schematic entry, simulation, reliability verification, and optimization for power, performance, area, timing, and yield. Develop integration specifications, behavioral models, electrical rule checkers, and timing and power models. Collaborate with SoC, RTL, verification, and physical design teams to deliver programmable logic solutions.

Architect and optimize timing and power implementation flows for ASIC/FPGA designs. Lead STA and UPF-based power flows, library generation/characterization, automation infrastructure, and apply ML/AI to improve flow efficiency, debug productivity, and signoff QoR while collaborating across PD, STA, library, and CAD teams.

Serve as the technical liaison between IT, Engineering, and Manufacturing to convert engineering needs into IT roadmaps, specs, user stories, and RFCs. Design high-level and component-level infrastructure (network, compute, storage, security, data), validate capacity and resilience, track dependencies and risks, chair working sessions, produce diagrams and decision records, manage backlog and roadmap, and provide status, KPI dashboards, and executive readouts.

Design, implement, and verify FPGA soft IP from micro-architecture through RTL coding, synthesis, P&R, STA, simulation, and hardware bring-up. Debug timing/CDC issues, develop testbenches, automate flows, and collaborate with software and hardware teams for system integration.

Develop and own manufacturing test content for FPGA reset/configuration and Secure Device Manager. Implement DFT strategies (scan, ATPG, MBIST, IJTAG), run pre-silicon test simulations, collaborate with RTL/DFT/verification teams, analyze test results and silicon failures, and optimize test time, cost, and yield.

Debug, troubleshoot, and resolve customer-reported FPGA/ASIC hardware, board, firmware, and system issues. Lead root-cause analysis and cross-functional corrective actions, coordinate with customers and manufacturing partners (including on-site visits), support product qualification and production ramp, and develop data collection for quality monitoring and continuous improvement.

Design and implement FPGA prototypes for ASIC validation, feature development, and high-speed interface verification. Develop Verilog RTL, integrate complex IP and memory interfaces, perform synthesis, place-and-route, timing closure, optimization, and hardware debugging. Lead board bring-up and validation, automate build and regression flows with Python, Tcl, or Bash, and collaborate with architecture, verification, firmware, and post-silicon teams to resolve issues and improve FPGA methodology.

Own the full FPGA Soft IP development lifecycle, including micro-architecture, RTL coding, synthesis, place-and-route, timing closure, simulation, verification, hardware bring-up, and lab debugging. Collaborate with embedded software, hardware, and systems teams on specifications, interfaces, and system integration. Develop reusable RTL, resolve clock-domain and timing issues, automate tool workflows, and validate designs on evaluation boards.

Manage end-to-end recruitment for FPGA roles across EMEA and India: source, screen, interview, negotiate offers, onboard candidates, maintain ATS records, report metrics, support employer branding and events, and ensure compliance and process improvements.

Develop, maintain, and enhance static timing analysis (STA) flows and tools; collaborate with CAD/DA and design teams on timing modeling and methodology improvements; write functional and test code, automate builds/deployments, and perform unit, integration, and end-to-end testing to ensure timing closure and robust flows.

Provide expert FPGA design guidance for video connectivity and high-speed serial interfaces (DisplayPort, MIPI, HDMI). Lead complex issue resolution, validate video IP examples and hardware platforms, create documentation and example designs, and collaborate with engineering and marketing to improve customer experience and product adoption.

Develops and validates IC testability and manufacturability from feasibility through production ramp. Designs test circuits, ATE test flows, performs device characterization and yield analysis, builds test hardware, debugs software to drive test equipment, and coordinates with fab, assembly, quality, and factory teams to enable high-volume manufacturing and optimize test cost and yield.

Design, simulate, verify, and optimize complex FPGA circuits, programmable logic, and IP (fabric, interconnect, clocking, memory, NoC). Lead microarchitecture definition, develop RTL/schematics/behavioral models, and drive cross-functional integration and PPA improvements. Mentor engineers, resolve complex design and silicon bring-up issues, and improve design methodologies across FPGA product generations.

Design, implement, and maintain application security in Oracle Fusion Cloud. Configure and customize job and duty roles, perform user provisioning and deprovisioning, troubleshoot access across SCM/Procurement/Inventory/OM/Finance, run SoD checks and remediation, generate security reports, maintain audit-ready documentation, support role cleanup and automation of provisioning workflows, and participate in role redesign and access reviews.

Define and drive Altera's security positioning across design, data, and supply chain security. Create external technical messaging, assets, and sales enablement; articulate value of FPGA-based crypto agility, SDM/root of trust, and PQC strategies. Analyze competitors, identify trends, and launch campaigns aligned to regulatory shifts to position Altera as a trusted security platform.

Designs RTL for FPGAs and ASICs, develops logic, simulates and verifies IP blocks and subsystems, defines microarchitecture, prototypes models, and collaborates with physical implementation and verification teams to meet power, performance, and area goals.

Design, develop, and support Oracle Fusion Cloud integrations, extensions, and reports across Finance and Supply Chain. Build OIC integrations, FBDI/ADFdi uploads, BI Publisher/OTBI reports, VBCS apps, and groovy-based extensions. Monitor ESS jobs and integrations, maintain technical documentation and runbooks, collaborate with functional teams and partners, and ensure change and release controls following Oracle best practices.

Develop and verify firmware algorithms for DDR5/LPDDR5 memory calibration on FPGA IP cores. Design architecture per protocol specs, implement firmware, integrate with CAD tools, perform verification, hardware bring-up, product release support, and provide customer technical support.