Jobs at Altera (altera.com)

Lead Altera's U.S. Government business strategy for defense, intelligence, aerospace, and federal customers. Build executive relationships, capture high-value opportunities (RFIs/RFPs/OTAs/SBIR), drive FPGA adoption, influence acquisitions, mentor BD teams, and coordinate cross-functional execution. Support growth, market intelligence, and representation at industry events; travel up to 30% and must be eligible for U.S. security clearance and export authorizations.

Lead OSAT technical engagement for NPI, yield ramp, qualification, and volume readiness for FPGA/SoC packaging and test. Optimize packaging/test architectures, drive yield/reliability/cost improvements, implement SPC and automation, manage supplier performance and reliability qualification to industry standards, and coordinate cross-functional root-cause and manufacturability efforts.

Support block- and top-level physical implementation for FPGA/ASIC products including floorplanning, placement, CTS, routing, STA/timing closure, power and congestion analysis, DRC/LVS verification, scripting/automation, cross-functional debugging, signoff readiness, and silicon bring-up support.

Drive thermal and electrical characterization and system-level validation of FPGA products, develop DFT and manufacturing test flows (ATPG, MBIST, BIST), analyze silicon and test data to close tester-to-system gaps, optimize yield and test time, and collaborate across design, packaging, manufacturing, and reliability teams.

Lead architecture and development of timing analysis, modeling, and optimization for the Quartus FPGA Compiler. Drive STA, timing closure, MCMM, PBA, timing modeling, and compiler infrastructure improvements. Mentor teams and collaborate across synthesis, placement, routing, and architecture to improve QoR, runtime, scalability, and signoff correlation for next-generation FPGA devices.

Lead the design and architecture of Linux kernel solutions for SoC/FPGA platforms, drive upstream contributions, and mentor junior engineers.

Lead the design of high-speed digital ASICs, collaborating with verification and back-end teams for implementation, timing closure, and post-silicon support.

The Senior Staff Verification Engineer collaborates to develop verification strategies, creates test plans, and implements verification environments; ensuring design functionality and robustness through testing and debugging.

The Aerospace & Defense Product Program Manager leads cross-functional teams to execute FPGA and platform programs, ensuring compliance with regulatory standards and managing program risks from concept to production.

Lead planning activities for next generation FPGA products, manage cross-functional teams, conduct market analysis, and communicate product roadmaps. Responsibilities include gathering customer requirements and driving innovation in product strategy.

The Product Development Engineer drives testability and manufacturability of ICs, develops thermal solutions, collaborates across teams, and ensures manufacturing readiness through data analysis and optimization.

Design, build, and productionize multi-agent, agentic AI systems to autonomously validate FPGA configuration and security firmware. Integrate agents with enterprise tools, implement RAG/vector DB pipelines, harden models with validation and cost controls, establish CI/CD and testing for LLM-driven workflows, and mentor engineers.

Support integration of SERDES IP into silicon, packages and PCBs. Perform channel, signal and power integrity simulations, review package/PCB layouts, debug failing simulations, and collaborate cross-team to meet SI/PI and performance goals.

The role involves functional logic verification of FPGA designs, developing verification plans, executing tests, analyzing designs for power and timing, and collaborating with various teams to enhance verification processes.

Responsible for verification tasks including creating test cases and test benches using UVM methodology, coordinating with cross-functional teams for full coverage verification.

The role involves verifying design architectures using UVM methodology, creating test cases, and coordinating with cross-functional teams for full coverage verification.

The engineer conducts FPGA logic verification, develops verification plans and test benches, runs simulations, debugs issues, and improves methodologies to ensure design specifications are met.

The Design Verification Engineer verifies FPGA design functionality, develops test plans, and collaborates with teams to ensure high-quality pre-silicon validation and verification.

The Performance Modeling Engineer will develop performance models for critical hardware components, analyze workloads, and collaborate with design teams to optimize system architecture.

The role involves verifying FPGA designs through system simulations, developing verification plans and test benches, debugging pre-silicon issues, and improving verification methodologies.