Jobs at Altera (altera.com)

Owns regional business development strategy for Physical AI, robotics, and drones across Europe and APAC. Leads strategic OEM and partner accounts, negotiates major multi-year deals, drives design wins, builds executive relationships and regional partner networks, manages pipeline and forecasting, and provides market intelligence. The role requires extensive semiconductor or embedded-systems business development experience, technical fluency across robotics and autonomous systems, strong regional industry networks, and approximately 40–50% travel.

Leads pre-silicon SoC, FPGA, and full-chip design verification for debug architectures. Develops SystemVerilog and UVM testbenches and test cases, defines verification strategies and plans, performs functional and performance verification, and coordinates with design, software, and architecture teams to achieve coverage. The role focuses on JTAG, USB, PCIe, ARM, and RISC debug architectures, with emulation and UltraSoC or Tessent experience advantageous.

Designs, administers, and optimizes Exchange Online, internal SMTP infrastructure, and Microsoft 365 messaging services. Responsibilities include mailbox and group management, mail flow troubleshooting, hybrid connectivity, service monitoring, email security, DLP, retention, eDiscovery, auditing, and legal holds. The role also supports migrations, compliance requirements, and third-party email security platforms.

Designs and manages Microsoft Intune endpoint management for Windows, macOS, iOS, and Android devices. Responsibilities include Autopilot provisioning, compliance and conditional access policies, application deployment, patching, security baseline development, Azure AD and Defender integration, troubleshooting endpoint issues, and maintaining documentation, dashboards, and runbooks.

Designs, deploys, and manages Microsoft Teams Rooms and unified communications infrastructure across office, laboratory, and manufacturing sites. Administers Teams conferencing, calling plans, Direct Routing, telephony integrations, meeting policies, and quality monitoring. Oversees room hardware, device health, standards, provisioning, and troubleshooting of audio/video and connectivity issues. Coordinates conference room installations with AV vendors and facilities teams while supporting hybrid collaboration best practices.

Design, deploy, and operate Azure Virtual Desktop infrastructure, including host pools, session desktops, RemoteApp environments, image pipelines, FSLogix profiles, scaling plans, security integrations, and GPU-enabled workloads. Monitor performance, resolve connectivity issues, optimize costs, collaborate with engineering and EDA teams, and maintain documentation and operational runbooks.

Designs, administers, and optimizes SharePoint Online, Microsoft Teams, and OneDrive for Business across a global workforce. Responsibilities include collaboration governance, permissions, information architecture, migrations, workflow automation, platform integrations, service monitoring, issue resolution, and end-user training. The role also manages external sharing, guest access, data classification, lifecycle policies, and Microsoft 365 platform health.

Leads the SRE function and team, establishing reliability practices, observability standards, automation, incident management, and 24x7 operations. Develops scalable monitoring and AIOps architectures, modernizes hybrid cloud and enterprise network connectivity, and partners with infrastructure, engineering, cybersecurity, and service providers. Provides architectural guidance, drives migration and continuous improvement, and reports reliability and operational maturity to leadership.

Design and implement high-performance Soft CPU cores optimized for Altera FPGA architectures. Responsibilities include processor microarchitecture, SystemVerilog/Verilog RTL, PPA optimization, FPGA synthesis, floorplanning, timing closure, configurable instruction extensions and caches, verification, simulation, and hardware validation. The role also involves collaboration with design verification teams and automation of FPGA compilation and regression workflows.

Leads the architecture and development of FPGA compiler and physical implementation technologies. Designs optimization algorithms for timing, area, power, routability, scalability, and runtime; integrates innovations into production tool flows; investigates customer implementation challenges; and provides technical leadership and mentorship. Collaborates with engineering, product management, and strategic customers while contributing to patents, publications, and the long-term roadmap of Altera’s FPGA software platform.

Lead the architecture, configuration, security, optimization, and scalability of the Workday HCM ecosystem across Core HCM, Compensation, Benefits, Absence, Talent, Recruiting, Reporting, and Security. Translate business requirements into sustainable Workday solutions, guide implementations and transformations, ensure data integrity and audit readiness, document designs, manage stakeholders, and mentor junior team members.

Responsible for timing closure and signoff of FPGA, SoC, and subsystem designs. Performs static timing analysis, derives interface timing constraints, conducts timing convergence analysis, and completes final timing signoff. Collaborates closely with design, architecture, and physical design teams. Requires expertise with industry-standard EDA tools, physical design and PNR flows, and timing signoff for 10nm or smaller technologies.

Leads planning and roadmap definition for next-generation FPGA devices and product families. Owns product prioritization, customer validation, product requirements, competitive and market analysis, and communication of roadmaps. Coordinates cross-functional teams across planning, architecture, engineering, marketing, applications engineering, sales, and business management from concept through mass production. Requires strong semiconductor expertise, customer engagement, leadership, analytical ability, and business acumen.

Develop and maintain high-level synthesis compiler infrastructure, including compiler passes, code transformations, and C/C++ to hardware compilation flows. Optimize compiler performance and resource usage for AI workloads, integrate and test new features, debug compiler outputs, and document technical work. The role also involves researching compiler technologies and collaborating with hardware and compiler engineers.

Lead enterprise network transformation across IT and business-unit lab environments. Define scalable, secure network architectures, routing and switching strategies, segmentation, migration plans, and hybrid connectivity between on-premises infrastructure and AWS or Azure. Collaborate with IT, engineering, cybersecurity, integration teams, and service providers; establish architecture standards, documentation, and best practices; guide implementation and troubleshooting; and drive automation, modernization, resilience, and operational efficiency.

Leads development, deployment, and continuous improvement of quality management systems for automotive and regulated semiconductor businesses. Serves as the subject-matter expert for IATF 16949, AIAG Core Tools, FMEA, APQP, PPAP, SPC, MSA, calibration, and measurement-system compliance. Partners cross-functionally with engineering, manufacturing, supply chain, quality, foundries, and OSATs; supports audits, certification readiness, corrective actions, training, and process governance across geographically distributed teams.

Develops EMEA embedded-business opportunities by building OEM, partner, and ecosystem relationships; translating FPGA and SoC requirements into solutions; leading technical workshops and proof-of-concept discussions; creating account and opportunity plans; supporting design wins and competitive displacement; and coordinating Field Sales, FAE, product, marketing, and engineering teams to drive pipeline, revenue, and long-term growth.

Lead the architecture, development, testing, and support of integrations across Blue Yonder supply chain platforms, PLM systems, Oracle Fusion ERP, and downstream Lakehouse or data warehouse environments. Build Python, SQL, ETL/ELT, and batch integrations; ensure data integrity, reconciliation, monitoring, and error handling; coordinate global stakeholders; manage integration backlogs; document data flows; and provide Tier-3 support for synchronization failures.

Supports FPGA and ASIC physical design implementation, including floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification, and signoff. Analyzes timing, power, congestion, and design rule reports; assists with ECOs, debugging, automation, silicon bring-up, and post-silicon support. Collaborates with RTL, DFT, CAD, verification, and other engineering teams to optimize designs for timing, power, area, and manufacturability.

Designs and validates FPGA implementations and embedded software features for customer applications using FPGA-SoC devices. Collaborates with silicon design, CAD tools, applications engineering, and product planning teams. The role involves hands-on work with hardware, software, development kits, digital design, and programming while supporting customer-focused solutions.