Jobs at Altera (altera.com)

Define and drive silicon domain subsystem architecture for next-generation FPGAs, focusing on security (Root of Trust, secure boot), FPGA configuration, microarchitectural features, hardware/software integration, validation/test planning, modeling and simulation, and cross-functional collaboration to deliver secure, high-performance, and power-efficient silicon solutions.

Lead functional logic verification of FPGA designs: develop verification plans, testbenches, and environments; execute simulations, debug pre-silicon issues, analyze power/timing, improve verification infrastructure, and collaborate with architects, RTL and physical design teams for coverage and integration.

The Storage Architect will design high-performance hybrid cloud storage solutions, optimize AWS storage, and lead NetApp architecture initiatives, while mentoring junior engineers and collaborating with cross-functional teams.

Perform physical design implementation of custom IP and SoC from RTL to GDS, including synthesis, place-and-route, CTS, floorplanning, STA, power/noise analysis, and layout verification. Lead verification and signoff (formal equivalence, STA, power integrity, DRC/LVS, reliability). Analyze results, fix violations, optimize power/frequency/area, and improve physical design methodologies and automation.

Develop and support DSP Builder and improve the HLD compiler stack. Analyze design bottlenecks, implement compiler optimizations, and benchmark FPGA-targeted generated hardware, combining compiler software development with digital hardware design.

Lead product development from pre-silicon design through post-silicon validation; define and optimize full-chip test methodologies and on-chip DFT strategies; drive technical innovation and process improvements; mentor and develop engineers; collaborate with global design, software, manufacturing, and product teams; and proactively manage technical risk to ensure product quality and timely delivery.

Define and drive architecture for high-speed external memory and general-purpose IO subsystems (DDR, LPDDR, MIPI, LVDS, ONFI). Lead cross-functional teams from concept through silicon bring-up, optimize PPA and usability with Quartus integration, perform trade-off analysis, and engage customers and partners to influence product roadmaps.

Develop and maintain automation and methodologies for EMIR analysis in silicon design, ensuring power integrity and reliability closure. Collaborate with cross-functional teams to define criteria and drive project-level signoff, while also evaluating and improving EMIR tools and methodologies.

Lead global teams in semiconductor hardware engineering, focusing on chip package and board development, power and reliability engineering, and strategic vendor management.

The FPGA Silicon Design Verification Engineer performs verification of FPGA designs, develops verification plans, analyzes simulations, debugs issues, and collaborates with teams to ensure functional compliance.

Define end-to-end robotics system architectures across sensing, perception, localization, planning, control and actuation. Lead customer technical engagements, deliver architecture proposals, PoC/prototyping, demos, and market strategy. Produce reference architectures, white papers, and training materials.

Develop and execute verification plans and UVM-based testbenches to validate RISC-V CPU microarchitecture. Perform functional coverage analysis, system-level simulations, debugging, automation with scripting, and collaborate with architects and RTL designers to close verification gaps and improve verification infrastructure.

Develop and validate full‑chip test methodologies and ATE programs for FPGA products, lead first‑silicon debug, collaborate cross‑functionally to optimize test, reduce cost, and ensure manufacturing and product quality. Convert and validate test patterns and develop test modules.

Develop and execute verification plans and UVM-based testbenches for FPGA/ASIC IP. Create directed and random tests, assertions, scoreboards, and coverage metrics; run simulations, debug failures, and automate flows with scripting.

Manage end-to-end customer relationships and lead-to-order processes for assigned accounts: forecast demand, execute orders, handle escalations, coordinate NPI/sample requests, maintain CRM data, prepare sales reports, and support cross-functional contract/pricing and onboarding activities to drive customer success.

Manage and grow the AMS SerDes layout team, own layout execution for AMS designs, coordinate with designers and program managers, drive quality and productivity improvements, handle headcount, performance, and career development, represent team in cross-functional reviews, and report status and risks to senior leadership.

Lead design and delivery of integrations between Blue Yonder planning platforms and upstream PLM (Windchill/Agile) and ERP (Oracle Fusion). Build and maintain ETL/ELT pipelines, Python/SQL-based integrations, batch scripts, and downstream lakehouse/data warehouse feeds. Ensure data integrity with validation, monitoring, and reconciliation; own integration testing, UAT, documentation, and Tier-3 support. Coordinate with global teams to translate requirements into integration designs and backlog user stories.

Design and implement transistor-level analog and mixed-signal circuits in advanced process nodes. Create floorplans, run detailed analog simulations, develop test plans, analyze silicon and pre-silicon results, and optimize circuits for power, performance, area, timing, yield, leakage, and signal integrity while collaborating with architecture and layout teams.

Lead and grow a distributed software IP engineering organization for FPGA platforms. Define technical strategy and roadmaps, deliver reusable IP, frameworks, drivers, and SDKs across AI, networking, DSP, security, and embedded domains. Partner with product, architecture, silicon, and customers to drive integration, quality, CI/CD, and ecosystem adoption while managing execution, metrics, hiring, and organizational performance.

Lead design and delivery of end-to-end Salesforce solutions across Sales Cloud, Revenue Cloud and CPQ. Own Lead-to-Quote architecture, build Agentforce/Claude agents, use AI-assisted tools like Cursor, define integrations with ERP, ensure compliance, lead discovery workshops, and support testing, enablement, and stakeholder alignment.