Jobs at Altera (altera.com)

Develop PCIe/CXL solutions for FPGAs, focusing on RTL design, integration, verification, and quality assurance for next-gen technologies.

The Logic Design Engineer will develop and optimize mixed-signal and high-speed IPs, focusing on RTL coding, simulations, integration, and hardware verification.

The Treasury Manager will oversee cash flow forecasting, manage global bank accounts, ensure compliance, and lead automation projects in the treasury department.

Lead and execute layout for digital, analog, and mixed-signal ICs. Perform floorplanning, placement, routing, and physical verification (DRC/LVS/ERC/RV). Collaborate with circuit designers, manage schedules, interface with foundries, drive design reviews, and mentor junior layout engineers.

The role involves developing and optimizing mixed-signal and high-speed IPs, RTL coding, simulation, and IP integration for full-chip designs.

Lead RTL-to-GDSII implementation for multiple design partitions, manage end-to-end physical design flow (synthesis-like, floorplanning, placement, custom pre-route), achieve timing closure and physical signoff, perform IR/RV, FEV, LVS/DRC checks, collaborate with custom macro teams, and resolve timing, congestion, and power issues independently.

Responsible for design validation of high-speed protocol IPs, creating verification plans, developing testbenches, and collaborating with teams for implementation and quality improvement.

As a verification engineer, you will design test strategies, build UVM infrastructure, analyze failures, and create test plans for functional correctness.

Develop test methods for chips and IPs, collaborate with teams, optimize tests for cost and quality, and validate test programs.

Develop and optimize mixed-signal and high-speed IPs, including RTL coding and simulation for full-chip designs, while collaborating across teams.

As a DFX Design Engineer, you will ensure manufacturability and testability of FPGA products, integrate hardware features for fault diagnostics, and develop automation scripts while collaborating with cross-functional teams.

We are looking for a college graduate to design and optimize layout for analog and mixed-signal integrated circuits, collaborating with experienced engineers on various tasks.

The DFT Design Engineer will implement DFT structures, generate test patterns, integrate debugging features, and collaborate with teams for silicon manufacturing.

The DFX Design Architect will lead strategy on DFT and DFD for high-performance FPGA designs, ensuring quality, cost optimization, and time-efficient design processes while mentoring engineering teams.

Join the semiconductor design team as an Analog Layout Design Engineer, focusing on optimizing layouts for analog and mixed-signal ICs, ensuring design verification, and collaborating with circuit designers.

The FPGA Silicon Design Engineer develops logic designs, coding, and simulation for FPGAs, participating in architecture definition and prototype creation, while ensuring power, performance, and area goals are achieved. They validate designs through verification and implement corrective actions for success in RTL tests.

Support Place and Route tools and methodologies for FPGA silicon design, improve flows, maintain tools, and provide user support.

The Internal Sales Representative supports the sales team through customer relationship management, order processing, opportunity management, and coordinating communications. Responsibilities include assisting customers, managing escalations, preparing sales reports, and onboarding new team members.

The Internal Sales Representative supports field sales by managing customer relationships, processing orders, and coordinating with cross-functional teams to enhance sales processes and outcomes.

The Internal Sales Representative supports field sales by managing customer relationships, processing orders, coordinating with cross-functional teams, and preparing sales reports.