Jobs at Altera (altera.com)

Designs, develops, deploys, and supports Boomi integration processes connecting ERP, supply chain, B2B, Windchill, and Datalake systems. Collaborates with stakeholders and technical teams to gather requirements, maintain RosettaNet and EDI integrations, troubleshoot workflows, and ensure performance, scalability, and security. Documents solutions, participates in code reviews, resolves issues, and provides technical guidance to junior team members.

Drive design wins and market expansion for FPGA-based Physical AI solutions across robotics, autonomous systems, industrial automation, and edge AI. Own market strategy, customer engagement, ecosystem partnerships, sales enablement, and cross-functional feedback to product and engineering. Support technical sales, produce reference architectures and ROI analyses, and convert opportunities into long-lifecycle platform wins.

Develop and maintain C++ and Python software models representing FPGA devices within Quartus Prime. Build high-performance APIs supporting synthesis, placement, routing, timing, and power analysis. Collaborate across hardware and software teams to integrate next-generation FPGA devices and create tools for FPGA device bring-up. The role requires strong software engineering, algorithms, data structures, communication, and experience with EDA or FPGA tools is preferred.

Develop production agentic AI systems using LLMs, tools, APIs, RAG pipelines, and multi-step reasoning workflows. Build reusable components for context management, tool integration, and knowledge retrieval. Evaluate model accuracy, latency, and cost while collaborating with FPGA and ASIC teams on hardware-aware AI optimization across CPU, GPU, and FPGA platforms.

Design and verify complex FPGA silicon using Verilog/SystemVerilog, execute ASIC physical design flows, optimize performance, power, and area, and support silicon bring-up and post-silicon debugging. Develop verification strategies with UVM and assertions, automate workflows with scripting, analyze timing and power, document technical work, and collaborate across architecture, verification, physical design, software, firmware, and product engineering teams.

Designs FPGA boards and development kits, creates board design guidelines and collateral, collaborates with cross-functional engineering teams on rollout plans, represents customer needs in product improvements, and provides technical support for board design issues. The role requires extensive semiconductor and FPGA board design experience, familiarity with FPGA interfaces and EDA tools, and strong communication and customer-engagement skills.

Leads end-to-end design and development of complex processor-, FPGA-, and ASIC-based hardware platforms. Translates system requirements into circuit specifications, schematics, PCB layouts, and design packages. Reviews high-speed routing, signal and power integrity, thermal simulations, BOM costs, and component availability. Drives board bring-up, power-on, debugging, validation, and cross-functional issue resolution across electrical, firmware, mechanical, thermal, and manufacturing domains.

Designs and validates FPGA RTL solutions for development kits and validation boards using Verilog or VHDL and Altera Quartus II. Develops Nios II embedded firmware in C/C++, performs board bring-up, hardware-software integration, timing closure, simulation, lab validation, and system-level debugging. The engineer investigates RTL, firmware, timing, clocking, memory, and peripheral issues; creates reusable components and automation; collaborates across engineering teams; documents designs and validation results; and provides technical guidance to less-experienced engineers.

Develop and execute system-level test plans for FPGA and multi-chip products. Build automated verification flows, regression scripts, and test content; analyze data and debug production or customer failures to root cause. Collaborate with hardware, software, silicon validation, manufacturing, and customer support teams to improve product quality, test coverage, manufacturability, and platform readiness. Document risk assessments, validation plans, user acceptance tests, and results.

Develop data pipelines and apply statistical analysis, machine learning, and deep learning to semiconductor system and analog design data. Build predictive models for circuit performance, reliability, and yield; design experiments; integrate solutions with design, verification, and test teams; and communicate findings through visualizations and reports. The role requires understanding semiconductor design flows, analog circuits, and system architectures.

Performs semiconductor physical design implementation from RTL through GDS, including synthesis, floorplanning, place and route, clock tree synthesis, timing closure, power and reliability analysis, verification, and signoff. Uses industry-standard EDA tools to optimize power, performance, and area, resolve design violations, support multiple power domains and DFT, and improve physical design methodologies and automation flows.

Leads architecture, RTL design, integration, verification, implementation, and silicon validation of high-speed interface IP for next-generation FPGA devices. Owns PCIe and related serial interface functionality, including PHY/PCS integration, equalization, link management, timing, synthesis, and formal verification. Collaborates across digital, analog, verification, software, and system teams; resolves complex design issues; leads technical reviews; and mentors engineers.

Develop and verify high-speed SerDes mixed-signal IP across digital, analog, DSP, and firmware-hardware systems. Responsibilities include constrained-random and coverage-driven verification, advanced verification environment development, DSP datapath validation, and root-cause analysis. The role involves the full verification lifecycle from specification through tape-out sign-off and uses AI-assisted engineering tools. Candidates should have a relevant bachelor’s degree and 0–3 years of hardware design or verification experience.

Develop and validate semiconductor products from concept through mass production. Responsibilities include defining product requirements, performing silicon validation and characterization, developing test hardware and software, analyzing yield and failures, debugging issues, documenting results, and improving development processes in collaboration with design, validation, and manufacturing teams.

Supports APAC corporate income, GST/VAT, withholding tax, transfer pricing, tax provision, reporting, filings, audits, and advisory activities. Coordinates statutory deadlines, documentation, reconciliations, and external advisors while partnering with Finance, Legal, HR, Payroll, Procurement, and IT. Improves tax processes, automation, controls, ERP data integrity, and documentation retention. Provides practical guidance on tax requirements, remote-work and permanent-establishment impacts, incentives, and tax-sensitive business initiatives across Malaysia, India, and other APAC jurisdictions.

Architects FPGA IP for O-RAN, eCPRI, and CPRI applications in 5G networks. Leads customer and partner technical discussions while managing FPGA IP software, validation, and architecture teams. Oversees design, RTL development, simulation, hardware validation, troubleshooting, and debugging. Sets goals, coaches employees, manages performance, and ensures teams deliver results. Requires expertise in FPGA development, wireless standards, timing closure, clock-domain crossing, reset architecture, and standard interfaces.

Designs and verifies synthesizable RTL and DSP algorithms for mixed-signal IP, including SerDes, ADC/DAC, calibration, equalization, and clock/data recovery systems. Responsibilities include microarchitecture, synthesis, timing closure, low-power design, AMS co-simulation, silicon bring-up, laboratory debugging, documentation, code reviews, and mentoring junior engineers. Collaborates closely with analog teams on digital-analog interfaces and adaptive control flows.

Lead end-to-end FPGA development kit execution across board architecture, RTL, firmware, validation, manufacturing, and supply chain. Coordinate global engineering teams, design partners, ODMs, contract manufacturers, and suppliers. Drive BOM planning, cost optimization, component availability, obsolescence management, technical risk resolution, manufacturing execution, and platform robustness improvements.

Manage and grow strategic OEM customer accounts, develop sales strategies, exceed revenue targets, provide tailored semiconductor solutions, and serve as the primary account contact. Collaborate with business solutions, product marketing, and engineering teams; monitor markets and competitors; and deliver forecasting, reporting, and analysis to senior leadership. The role focuses on complex technical sales cycles and long-term customer relationships in the Los Angeles area.

Designs and develops analog circuits for advanced semiconductor process nodes and mixed-signal IPs. Responsibilities include circuit simulation, verification, floorplan optimization, layout review, test-plan development, and optimizing designs for power, performance, area, timing, and yield. The engineer collaborates with architecture, layout, and verification teams, tracks design issues, reports progress, and drives technical resolutions.