Jobs at Altera (altera.com)

Leads end-to-end architectures for Physical AI systems spanning robotics, drones, medical, industrial, and quantum computing applications. Designs low-latency sense-think-act pipelines across CPU, GPU, and FPGA platforms; leads customer engagements, technical presentations, solution roadmaps, PoCs, prototypes, market strategy, reference architectures, and technical content.

Designs and owns architecture, microarchitecture, and parameterizable RTL for high-performance FPGA soft IP, including AMBA AXI interconnects. Responsibilities include timing, power, congestion, CDC/RDC analysis, verification collaboration, regression debugging, customer technical support, and mentoring engineers. Requires deep AXI4 expertise, FPGA implementation and simulation tool proficiency, and scripting skills for automation.

Design, develop, and optimize software for FPGA electronic design automation tools, including synthesis, placement, routing, timing analysis, and compilation. Build scalable algorithms, improve performance and resource utilization, debug complex issues, and collaborate with architecture, CAD, verification, and product teams. Contribute to software architecture, testing, CI/CD, code reviews, and research into EDA and AI-assisted design optimization.

Manages pricing governance, quoting support, commercial operations, master data, compliance, reporting, and business systems. The role validates transactions, maintains pricing accuracy, supports audits, develops dashboards, analyzes revenue impacts, defines system requirements, coordinates UAT, drives automation, and leads cross-functional process and technology initiatives.

Designs FPGA example solutions and technical assets using Quartus tools, supports customers by debugging and resolving design issues, evaluates product features, develops unit tests, and improves customer journeys. The role also creates training materials, AI skills, and agents to accelerate customer design workflows. Requires FPGA design, simulation, debugging, signal analysis, development board, and minimal software experience.

Leads global financial consolidation and reporting across multinational entities, overseeing close processes, intercompany accounting, foreign currency translation, consolidated statements, controls, audits, and process automation. Partners with finance, IT, procurement, tax, treasury, and regional teams to improve reporting quality, compliance, and close predictability while supporting technical accounting initiatives and leading distributed teams.

Supports corporate FP&A through budgeting, forecasting, financial modeling, P&L analysis, variance reporting, dashboard development, and workforce cost tracking. Partners with finance and business stakeholders, responds to ad hoc analytical requests, maintains planning and reporting systems, improves financial processes, and contributes to finance transformation initiatives.

Leads FPGA configuration enablement, product development, hardening, and customer support. Responsibilities include debugging configuration issues, developing and validating FPGA design examples, creating technical documentation and training, advising on configuration solutions, and driving product improvements. The role requires board bring-up, systematic hardware debugging, digital logic and FPGA experience, and programming knowledge in languages such as Verilog, VHDL, C, or Python.

Develops and integrates DFT solutions for complex ICs, including SCAN, MBIST, BSCAN, ATPG, RTL, simulation, verification, and timing closure. Optimizes designs for test coverage, manufacturing efficiency, and physical implementation. Collaborates with architecture, verification, manufacturing, and post-silicon teams to support IP and SoC integration, silicon debug, mixed-signal DFT, and test content delivery.

Design complex analog circuit layouts and perform comprehensive verification for design rules, electromigration, IR drop, ESD, and reliability. Plan floorplans, power grids, bumps, shielding, and signal matching while optimizing area, power, reliability, and performance. Develop layout methodologies, troubleshoot design and tool-flow issues, and collaborate with circuit, process technology, and package design teams to meet specifications.

Leads application engineering for Agilex FPGA devices, resolving customer escalations, supporting field teams, developing reference designs and technical collateral, delivering training, and collaborating with global R&D and design teams. Requires expertise in RTL design flows, FPGA/ASIC processes, timing closure, Quartus methodologies, and complex system-level problem solving involving 5G and DSP technologies.

Design and implement DFT architectures for complex semiconductor products, including FPGA, processor, DSP, SERDES, IO, and multi-die designs. Responsibilities include defining specifications, inserting test logic, generating ATPG patterns, applying timing constraints, validating designs pre-silicon, and supporting silicon bring-up and debug. The engineer will collaborate with IP, integration, and test development teams while improving DFT automation, test coverage, manufacturing yield, test cost, and production readiness.

Leads global SOC and incident response operations, including monitoring, alert triage, investigations, detection engineering, escalation, playbooks, metrics, and major incident coordination. The role improves security operations through SIEM, SOAR, EDR/XDR, automation, threat intelligence, threat hunting, and MITRE ATT&CK-aligned detections. It oversees SOC workflows, global handoffs, managed security providers, incident readiness exercises, and cross-functional collaboration while ensuring processes satisfy governance, regulatory, privacy, and audit requirements.

Lead enterprise identity and access management, privileged access management, and data loss prevention programs. Establish security governance, lifecycle controls, privileged account protections, data classification, DLP policies, incident response, compliance reporting, and continuous improvement. Partner with cross-functional teams to reduce security risks, improve control effectiveness, and strengthen enterprise security maturity across corporate systems, cloud environments, sensitive semiconductor data, source code, and intellectual property.

Develops timing methodologies and executes full-chip timing for advanced FPGA products. Responsibilities include timing modeling, integration and validation, clocking and timing constraint development, STA and SPICE correlation, extraction analysis, timing signoff, quality checks, and technical issue resolution. The role collaborates with front-end, back-end, and cross-functional teams to improve timing processes and deliver complex semiconductor designs on aggressive schedules.

Owns financial planning and analysis for engineering and R&D cost centers, including annual operating plans, quarterly forecasts, spend tracking, and financial close. Builds investment models, supports NPV and ROI analysis, translates technology roadmaps into long-term forecasts, and partners with engineering, accounting, and business leaders on investment decisions, contracts, licensing, and royalty-related financial treatment.

Leads end-to-end architecture and delivery of Physical AI systems spanning sensors, perception, planning, control, actuation, and heterogeneous CPU/GPU/FPGA compute. Drives customer engagements, technical proposals, proof-of-concepts, prototypes, market strategy, reference architectures, and technical content. Requires extensive robotics or AI systems experience, real-time deterministic processing expertise, and familiarity with ROS/ROS2, sensor fusion, localization, motion planning, world modeling, and VLA/VLM models.

Leads semiconductor product development from pre-silicon design through post-silicon validation, defining full-chip test methodologies and on-chip DFT strategies. Drives technical innovation, risk mitigation, process improvement, and cross-functional collaboration across design, software, manufacturing, and product engineering. Mentors engineers and resolves complex technical challenges while ensuring product testability, performance, quality, and production readiness.

Defines and scales security assurance and global compliance practices across engineering and product teams. Establishes SDL requirements, lifecycle checkpoints, controls, evidence plans, and reporting. Conducts security reviews, CRA assessments, readiness reviews, and security hackathons; coordinates certification activities with notified bodies and stakeholders. Supports FPGA customers with security and certification requirements, tracks remediation, validates corrective actions, and reports progress to technical and executive audiences.

Design, verify, optimize, and deliver reusable FPGA RTL IP for robotics and industrial automation. Develop sensor-processing, fusion, DSP, and compute accelerator pipelines; define HAL and driver APIs; integrate designs using Quartus Prime and Platform Designer; perform simulation, timing closure, CDC analysis, and on-chip debugging. Collaborate on hardware/software co-design, robotics platform integration, continuous integration, board bring-up, reference designs, documentation, and customer issue resolution.