Jobs at Altera (altera.com)

Lead complex FPGA device development programs from definition through production rollout. Coordinate silicon, IP, software, firmware, validation, manufacturing, and globally distributed engineering teams. Manage schedules, milestones, dependencies, risks, resource constraints, and critical paths. Improve program management processes, provide executive status reporting, and support silicon bring-up, validation, sampling, and production readiness. Influence cross-functional stakeholders and drive accountability without direct authority.

Develop and validate full-chip test methodologies for FPGA products, including on-chip DFT, test vectors, coverage analysis, ATE programs, silicon debug, and test optimization. The role develops HMDT and UFP test modules, converts STIL patterns to pobj, validates tester programs, supports manufacturing efficiency, collaborates globally across engineering teams, and mentors engineers.

Lead cross-functional programs securing and maintaining Malaysian government approvals, incentives, grants, and regulatory compliance. Manage project plans, milestones, risks, documentation, submissions, government queries, stakeholder meetings, and audit-ready evidence. Coordinate engineering, finance, HR, legal, tax, procurement, and corporate affairs teams while engaging Malaysian agencies, consultants, and senior executives.

The AppSec/DevSecOps Engineer embeds security across the software development lifecycle, implementing SAST, DAST, SCA, secrets, container, API, and infrastructure-as-code controls in CI/CD pipelines. Responsibilities include threat modeling, secure architecture and code reviews, cloud and software supply-chain security, vulnerability assessment and remediation, security automation, dashboards, risk reporting, developer training, and secure SDLC improvement across Azure, AWS, Kubernetes, and hybrid environments.

Lead complex FPGA and semiconductor product development programs from product definition through production. Drive strategy, roadmaps, milestones, risk mitigation, cross-functional alignment, executive reporting, and technical readiness across architecture, silicon, hardware, software, firmware, validation, and manufacturing teams. The role requires influencing distributed engineering organizations, resolving technical and organizational challenges, improving program governance, and mentoring other technical program leaders.

Leads enterprise infrastructure cyber defense across network, cloud, on-premises, hybrid, and engineering environments. Oversees network and cloud security, application security, DevSecOps, vulnerability management, security architecture, risk assessments, cyber resilience, governance, and executive reporting. Partners across Security, IT, Engineering, Compliance, Legal, and Audit to establish controls, improve visibility, reduce vulnerability exposure, strengthen resilience, and develop security capabilities. Requires hands-on leadership across Azure, AWS, infrastructure protection, secure SDLC, and security testing.

Develop and deploy manufacturing test solutions for advanced FPGA products from test architecture through production release. Define DFT strategies, generate test vectors, analyze coverage, develop and debug ATE programs, support silicon bring-up and production ramp, and investigate yield and failure data. The role also involves tester validation, pattern conversion, production qualification, test optimization, and collaboration with design, software, product engineering, DFT, and manufacturing teams.

Owns regional business development strategy for Physical AI, robotics, and drones across Europe and APAC. Leads strategic OEM and partner accounts, negotiates major multi-year deals, drives design wins, builds executive relationships and regional partner networks, manages pipeline and forecasting, and provides market intelligence. The role requires extensive semiconductor or embedded-systems business development experience, technical fluency across robotics and autonomous systems, strong regional industry networks, and approximately 40–50% travel.

Leads pre-silicon SoC, FPGA, and full-chip design verification for debug architectures. Develops SystemVerilog and UVM testbenches and test cases, defines verification strategies and plans, performs functional and performance verification, and coordinates with design, software, and architecture teams to achieve coverage. The role focuses on JTAG, USB, PCIe, ARM, and RISC debug architectures, with emulation and UltraSoC or Tessent experience advantageous.

Designs, administers, and optimizes Exchange Online, internal SMTP infrastructure, and Microsoft 365 messaging services. Responsibilities include mailbox and group management, mail flow troubleshooting, hybrid connectivity, service monitoring, email security, DLP, retention, eDiscovery, auditing, and legal holds. The role also supports migrations, compliance requirements, and third-party email security platforms.

Designs and manages Microsoft Intune endpoint management for Windows, macOS, iOS, and Android devices. Responsibilities include Autopilot provisioning, compliance and conditional access policies, application deployment, patching, security baseline development, Azure AD and Defender integration, troubleshooting endpoint issues, and maintaining documentation, dashboards, and runbooks.

Designs, deploys, and manages Microsoft Teams Rooms and unified communications infrastructure across office, laboratory, and manufacturing sites. Administers Teams conferencing, calling plans, Direct Routing, telephony integrations, meeting policies, and quality monitoring. Oversees room hardware, device health, standards, provisioning, and troubleshooting of audio/video and connectivity issues. Coordinates conference room installations with AV vendors and facilities teams while supporting hybrid collaboration best practices.

Design, deploy, and operate Azure Virtual Desktop infrastructure, including host pools, session desktops, RemoteApp environments, image pipelines, FSLogix profiles, scaling plans, security integrations, and GPU-enabled workloads. Monitor performance, resolve connectivity issues, optimize costs, collaborate with engineering and EDA teams, and maintain documentation and operational runbooks.

Designs, administers, and optimizes SharePoint Online, Microsoft Teams, and OneDrive for Business across a global workforce. Responsibilities include collaboration governance, permissions, information architecture, migrations, workflow automation, platform integrations, service monitoring, issue resolution, and end-user training. The role also manages external sharing, guest access, data classification, lifecycle policies, and Microsoft 365 platform health.

Leads the SRE function and team, establishing reliability practices, observability standards, automation, incident management, and 24x7 operations. Develops scalable monitoring and AIOps architectures, modernizes hybrid cloud and enterprise network connectivity, and partners with infrastructure, engineering, cybersecurity, and service providers. Provides architectural guidance, drives migration and continuous improvement, and reports reliability and operational maturity to leadership.

Design and implement high-performance Soft CPU cores optimized for Altera FPGA architectures. Responsibilities include processor microarchitecture, SystemVerilog/Verilog RTL, PPA optimization, FPGA synthesis, floorplanning, timing closure, configurable instruction extensions and caches, verification, simulation, and hardware validation. The role also involves collaboration with design verification teams and automation of FPGA compilation and regression workflows.

Leads the architecture and development of FPGA compiler and physical implementation technologies. Designs optimization algorithms for timing, area, power, routability, scalability, and runtime; integrates innovations into production tool flows; investigates customer implementation challenges; and provides technical leadership and mentorship. Collaborates with engineering, product management, and strategic customers while contributing to patents, publications, and the long-term roadmap of Altera’s FPGA software platform.

Lead the architecture, configuration, security, optimization, and scalability of the Workday HCM ecosystem across Core HCM, Compensation, Benefits, Absence, Talent, Recruiting, Reporting, and Security. Translate business requirements into sustainable Workday solutions, guide implementations and transformations, ensure data integrity and audit readiness, document designs, manage stakeholders, and mentor junior team members.

Responsible for timing closure and signoff of FPGA, SoC, and subsystem designs. Performs static timing analysis, derives interface timing constraints, conducts timing convergence analysis, and completes final timing signoff. Collaborates closely with design, architecture, and physical design teams. Requires expertise with industry-standard EDA tools, physical design and PNR flows, and timing signoff for 10nm or smaller technologies.

Leads planning and roadmap definition for next-generation FPGA devices and product families. Owns product prioritization, customer validation, product requirements, competitive and market analysis, and communication of roadmaps. Coordinates cross-functional teams across planning, architecture, engineering, marketing, applications engineering, sales, and business management from concept through mass production. Requires strong semiconductor expertise, customer engagement, leadership, analytical ability, and business acumen.