Jobs at Altera (altera.com)

The Junior Logic Design Engineer will assist in logic design and RTL development, support architectural discussions, and collaborate on verification activities while gaining hands-on experience in a team environment.

Responsible for verifying Design for Debug architecture, creating test cases and test benches using UVM. Coordinate cross-functional efforts for full coverage verification.

Lead DFT architecture and strategy, oversee complex DFT implementation, ensure sign-off quality, and mentor engineers. Drive collaboration across multiple teams, optimize power and timing, and provide leadership in functional safety and quality efforts.

The Technical Program Manager leads complex technical programs for FPGA device development, coordinating efforts across various engineering disciplines, managing schedules, and ensuring global team alignment.

Lead SoC architecture verification by developing strategies and test cases using UVM. Coordinate with teams to achieve verification goals and document verification plans.

As an Analog Layout Design Engineer, you will create complex analog layouts, lead multiple layout blocks, and ensure design verification across various criteria.

Develop and optimize mixed-signal and high-speed IPs, ensure design integrity, performance optimization, and provide customer support for integration.

The Sr. SoC Design Verification Engineer is responsible for SoC architecture verification, creating test cases and test benches using UVM, coordinating efforts across teams to achieve verification goals.

Lead and own DFT architecture and strategy for advanced FPGA/SoC/multi‑die platforms. Architect scan, ATPG, compression, MBIST/LBIST, IJTAG/JTAG, and production test flows; drive DFT methodology, cross‑functional integration, silicon debug, yield and manufacturing test optimization; mentor teams and partner with EDA vendors to deploy scalable automation and tools.

As a Senior DFT Design Engineer, you will define and implement DFT architectures, perform test logic insertion, collaborate with design teams, and contribute to DFT methodologies.

Develop and optimize FPGA routing algorithms within the compiler toolchain. Improve performance, routability, timing closure, and scalability. Collaborate with architecture, synthesis, timing, and hardware teams; debug routing congestion and integrate features into the compiler infrastructure.

Develop and execute verification strategies and UVM-based testbenches for IP blocks in SoCs/FPGAs. Create directed and constrained-random tests, SVA assertions, and formal checks; run regressions, debug failures, track coverage metrics, and automate verification flows with scripting.

Lead the design and development of FPGA-centric solutions for robotics and industrial automation, while mentoring a skilled engineering team and engaging with customers.

Oversee and mentor a GUI development team, coordinating global efforts and collaborating with various teams to deliver EDA tools.

Lead enterprise Quality Management System for FPGA design, ensuring compliance with standards like ISO 9001 and AS9100D. Oversee audits, issue management, and drive continuous improvement.

The Sales Account Manager provides technical expertise to close sales opportunities, manages customer relationships, drives revenue growth, and analyzes data to resolve customer issues.

Lead full-cycle recruiting for FPGA roles: partner with hiring managers, source and screen niche technical candidates, manage interviews and offers, maintain ATS records, track hiring metrics, and support employer branding and compliance.

Lead support and enhancements for Oracle Fusion ERP Record to Report and Acquire to Retire processes. Analyze and optimize GL, Fixed Assets, Intercompany and Cost Accounting workflows; design solutions, manage integrations (Bloomberg, Workday, Oracle EPM), provide application support, create documentation, and lead regression and UAT testing with global stakeholders.

Design, develop, and deploy AI-driven applications (LLMs, RAG, agentic AI, MCP) and REST APIs. Build backend components, data pipelines, and relational storage. Implement solutions in Python/C++/C#, use Git/GitHub workflows, perform prompt engineering, model evaluation, troubleshooting, and collaborate with cross-functional teams to automate workflows.

Design, implement, and validate FPGA configuration architecture and subsystems. Develop configuration RTL/firmware and interfaces, support JTAG/SPI/CvP schemes, debug bitstream and bring-up issues, collaborate across architecture, software, and validation teams, and maintain specifications and test documentation.