Jobs at Altera (altera.com)

Leads end-to-end architectures for Physical AI systems spanning robotics, drones, medical, industrial, and quantum computing applications. Designs deterministic Sense-Think-Act pipelines across sensors, AI, real-time control, and CPU/GPU/FPGA hardware. Drives customer engagements, technical presentations, proof-of-concepts, solution roadmaps, competitive analysis, reference architectures, and market development. Contributes to technical publications and training materials.

Supports APAC and EMEA indirect tax compliance, including GST, VAT, SST, withholding tax, reconciliations, reporting, audits, and advisory queries. Partners with Finance, Accounting, Procurement, IT, and external advisors to meet filing deadlines, improve tax workflows and ERP setup, resolve cross-border tax matters, and support corporate income tax compliance and provisions.

Supports semiconductor product development through lab equipment qualification, tester and thermal-system monitoring, engineering validation, hardware/software troubleshooting, equipment upgrades, calibration, and test-flow debug. Maintains lab infrastructure, tracks materials, documents technical findings, coordinates escalations, and identifies automation opportunities for recurring engineering tasks. Collaborates with product engineers, test engineers, and lab operations while following safety, equipment-handling, and documentation requirements.

Develop and maintain semiconductor device behavioral models for EDA circuit simulation tools. Validate models against experimental and simulation data, document usage and performance, support design and verification teams, explore new modeling techniques, and collaborate with EDA vendors and software teams to improve modeling tools and flows.

Supports financial planning, forecasting, reporting, and month-end close activities. Develops models for expenses, headcount, capital expenditures, and initiatives; analyzes variances and KPIs; prepares management reporting and executive presentations; evaluates investments and cost-saving opportunities; improves planning systems and processes; and partners with Finance, Accounting, Supply Chain, Engineering, and business leaders to drive operational efficiency and performance.

Leads semiconductor product development, testability, manufacturability, characterization, yield analysis, and production ramp activities. Develops and debugs ATE test methods, software, and hardware; resolves equipment and product issues; drives DFT, DFM, test-time reduction, and manufacturing readiness. Coordinates with design, fab, assembly, OSAT, quality, reliability, and factory teams to support NPI, qualification, capacity planning, and high-volume manufacturing. Requires extensive wafer sort and semiconductor test equipment expertise.

Develop and optimize C/C++ software tools for Altera’s Quartus FPGA programming environment. Responsibilities include FPGA peripheral placement and mapping, device-modeling automation, hardware/software co-design, CAD and compilation tasks, and feature development within a large codebase. The role involves close collaboration with FPGA silicon and IP, customer requests, and software abstractions for acceleration applications.

Develop and enable embedded FPGA products, with emphasis on device security and post-quantum cryptography. Responsibilities include product hardening, customer technical support, security prototyping, application software development, benchmarks, training collateral, workload definition, and product improvement. The role requires expertise in embedded processors and system design, with preferred experience in cryptography, secure boot software, operating systems, FPGA development, processor and board debugging, and hardware security.

Designs and improves security across Azure and AWS environments, including cloud architecture, IAM, networking, workloads, infrastructure as code, automation, monitoring, detection, incident response, vulnerability management, and governance. The role establishes guardrails and secure standards, embeds controls into CI/CD, investigates cloud security events, supports compliance, and mentors engineers while partnering with platform, infrastructure, application, identity, and security operations teams.

Leads enterprise network security strategy, architecture, and roadmap across on-premises, cloud, data center, laboratory, campus, WAN, and hybrid environments. Designs Zero Trust, segmentation, firewall, ZTNA, SASE, SD-WAN, detection, telemetry, and automation solutions. Provides senior incident-response expertise, conducts architecture and risk assessments, supports audits, establishes standards and governance, and mentors engineers while advising technical and executive stakeholders.

Design, implement, verify, and optimize synthesizable RTL for FPGA and programmable hardware solutions supporting AI acceleration and Physical AI applications. Develop microarchitectures, datapaths, control logic, and accelerator architectures; support synthesis, timing closure, debugging, hardware-software integration, and system bring-up. Collaborate with architecture, verification, firmware, software, and physical design teams to deliver high-performance, scalable computing solutions for robotics, autonomous systems, machine vision, and edge AI.

Leads financial planning and analysis for a business division, including strategic planning, budgeting, forecasting, variance analysis, and performance reporting. Partners with leadership and business unit heads to optimize costs, allocate resources, improve productivity, and support revenue and profitability goals. Oversees automated business intelligence reporting and develops team capabilities while driving accountability and organizational results.

Leads annual planning, forecasting, long-range financial planning, financial modeling, variance analysis, executive reporting, investment evaluation, and performance management. Partners with senior leadership and cross-functional teams to guide strategic decisions, resource allocation, IPO readiness, and financial process improvements. Supports board and investor presentations while improving reporting frameworks and forecast accuracy.

Provides hands-on technical leadership for RTL architecture, microarchitecture, implementation, integration, verification, and delivery of FPGA and programmable SoC subsystems. Leads high-performance datapath, memory, interconnect, packet-processing, and acceleration designs while balancing power, area, timing, reliability, and schedule. Establishes RTL methodologies, drives cross-functional technical execution, resolves complex design issues, and mentors engineers across global teams.

Lead architecture, microarchitecture, RTL development, integration, verification support, timing closure, bring-up, and performance characterization for FPGA and programmable SoC subsystems. Translate system requirements into scalable digital designs, drive tradeoffs across performance, power, area, and reliability, and resolve complex cross-functional issues. Establish reusable IP, coding standards, automation, and quality practices while mentoring engineers and influencing technical roadmaps across global hardware, software, verification, and product teams.

Leads functional safety architecture for semiconductor and IP development across avionics, automotive, defense, space, and industrial markets. Defines safety concepts, mechanisms, requirements, and architectures; performs FMEA, FMEDA, FTA, and DFA analyses; guides ASIL/SIL decomposition and verification strategies; and ensures diagnostic coverage and safety certification. Collaborates across hardware, software, design, verification, and external assessment teams to produce safety cases and achieve ISO 26262, IEC 61508, and related compliance.

Lead the architecture and development of agentic AI systems integrating LLMs, RAG, multi-agent orchestration, and hardware acceleration. Design scalable production AI platforms, optimize LLM inference for FPGA and ASIC systems, and guide hardware-software co-design across heterogeneous computing environments. Provide technical leadership through architecture reviews, mentoring, and cross-functional collaboration while advancing AI and semiconductor integration.

Develop production agentic AI systems using LLMs, tools, APIs, RAG pipelines, and multi-step reasoning workflows. Build reusable components for context management, tool integration, and knowledge retrieval. Evaluate model accuracy, latency, and cost while collaborating with FPGA and ASIC teams on hardware-aware AI optimization across CPU, GPU, and FPGA platforms.

Develops and optimizes mixed-signal and high-speed IP for full-chip integration. Responsibilities include RTL coding, logic design, simulation, synthesis optimization, IP integration and release, hardware bring-up, verification, and debugging. The role also creates design and simulation examples and collaborates across teams to meet IP release requirements.

Develops and validates manufacturing test content for FPGAs to detect defects, improve test coverage and yield, and optimize test time and cost. Responsibilities include DFT strategy, scan insertion, MBIST, ATPG, test pattern development, RTL integration, pre-silicon simulation, silicon failure analysis, customer return investigation, and collaboration with manufacturing and test teams.