Physical Design Engineer

Job Details:

Job Description: 

The Role and Impact

• The HIPD SAM team is responsible for delivering end-to-end Physical Design and Analog Layout for Intel's Client, Server and ASIC Hard-IP portfolios, as well as advanced testchips for IP and SoC functional blocks. The team supports implementation from RTL/Netlist through GDSII and executes using established Physical Design methodologies and sign-off practices.
• As Physical Design Engineer (Grade 8) By leveraging your expertise, you will directly impact Intel's innovation pipeline, improving product-level parameters such as power, frequency, and area, ensuring our designs deliver exceptional performance and reliability. Join us in driving technology forward and advancing Intel's mission to create world-changing innovation.

Key Responsibilities
- Execute physical design implementation from RTL to GDS, including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, and power/clock distribution.
- Conduct verification and signoff, including formal equivalence verification, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and timing analysis.
- Identify and resolve violations, making recommendations for current and future product architectures.
- Optimize designs to enhance metrics such as power, frequency, and area using industry-standard EDA tools.
- Develop and improve physical design methodologies, automation flows, and processes.
- Possess expertise in structural and physical design, including timing closure, physical clock design, and multiple power domain analysis.
- Define and apply constraints for hierarchical design integration and floor planning concepts.
- Collaborate with cross-functional teams to ensure designs meet Intel's quality and performance standards.

Qualifications:

Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 6+ years of relevant experience; or Master's degree in Electrical Engineering, Microelectronics, or VLSI with 4+ years of relevant experience; or PhD with 2+ years of relevant experience.
- Proficiency in RTL-to-GDS flow, including synthesis, placement, routing, and design-for-test using industry-standard EDA tools.
- Advanced knowledge in timing methodology, constraints development, and timing convergence challenges.
- Hands-on experience with low-power designs, multiple power domains, and layout verification.
- Expertise in scripting languages such as Perl, TCL, or Python to enhance automation and design efficiency.
Preferred Qualifications
- Strong understanding of VLSI circuits, sub-micron CMOS technologies, and design techniques for high-speed, low-power digital circuits.
- Experience in computer architecture, logic design fundamentals, and hardware description languages such as Verilog or System Verilog.
- Leadership experience, including mentorship and driving teams toward success.
- Proven track record of delivering successful projects with complex design challenges.
Apply now to join Intel's world-class engineering team and become a driving force behind tomorrow's technological breakthroughs.

          

Job Type:Experienced Hire

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.