Physical Design Engineer

This role is for one of the Weekday's clients

Min Experience: 5+ years

Location: Bengaluru
JobType: full-time

We are seeking an experienced Lead Physical Design Engineer to drive the complete ASIC physical design flow from RTL to GDSII. The ideal candidate will have strong expertise in synthesis, place and route (PNR), timing closure, signoff, and physical verification while leading a team of engineers on complex semiconductor projects.

In this role, you will be responsible for delivering high-quality silicon implementations, optimizing designs for performance, power, and area (PPA), and ensuring successful tape-out through close collaboration with RTL, STA, DFT, Analog, and Verification teams.

• Lead the complete RTL-to-GDSII implementation flow for complex ASIC and SoC designs.
• Execute and oversee synthesis, floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical implementation.
• Drive design planning activities, including partitioning, macro placement, bump planning, and routing strategies.
• Optimize designs for timing, power, congestion, and area while achieving design closure.
• Perform physical verification and signoff, ensuring compliance with design and manufacturing requirements.
• Work closely with RTL, STA, DFT, Analog, and Verification teams to resolve implementation challenges.
• Integrate analog and mixed-signal IP blocks into digital designs while maintaining design quality.
• Develop and optimize power grids and support low-power implementation methodologies.
• Execute timing closure using ECO methodologies and optimize design performance.
• Perform signoff activities, including Logical Equivalence Check (LEC), Reliability Verification (RV), Layout Verification (LV), Static Timing Analysis (STA), power analysis, and low-power verification.
• Debug complex implementation and signoff issues to ensure successful tape-out.
• Lead, mentor, and manage a team of physical design engineers while driving project execution and delivery.
• Coordinate with cross-functional stakeholders to ensure project milestones and quality objectives are achieved.

• Strong experience in the complete RTL-to-GDSII physical design flow.
• Expertise in ASIC Physical Design, including synthesis and Place & Route (PNR).
• Hands-on experience with Fusion Compiler and/or Cadence Innovus.
• Strong knowledge of:
• Macro placement
• Floorplanning
• Power planning and power grid creation
• Placement
• Clock Tree Synthesis (CTS)
• Routing
• Experience with design planning, partitioning, bump planning, and routing methodologies.
• Strong understanding of Static Timing Analysis (STA) and timing closure.
• Expertise in physical verification and signoff methodologies.
• Experience with:
• LEC (Conformal)
• RV (Ansys)
• Layout Verification (Calibre DRC/LVS)
• PTPX
• VCLP (VC Static Checks)
• PrimeTime ECO / Tweaker
• Experience implementing low-power designs.
• Knowledge of ESD verification and signoff flows.
• Strong debugging and problem-solving skills.
• Proven experience leading engineering teams of approximately 10 or more members.
• Experience integrating analog blocks into digital SoC designs.

• Experience managing complete RTL-to-GDSII implementation projects.
• Exposure to advanced semiconductor technology nodes.
• Familiarity with automation using TCL, Python, or Perl scripting.
• Knowledge of EMIR analysis and power integrity methodologies.
• Experience with advanced packaging or chiplet-based designs.

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
• 5–7 years of experience in ASIC Physical Design and implementation.
• Proven experience delivering successful ASIC or SoC tape-outs.
• Experience leading physical design teams in complex semiconductor development programs.

• Strong technical leadership and mentoring abilities.
• Excellent analytical and debugging skills.
• Outstanding problem-solving capabilities.
• Strong communication and stakeholder management skills.
• Ability to manage multiple projects and priorities in a fast-paced environment.
• Collaborative mindset with experience working across cross-functional engineering teams.

Success in this role will be measured by the successful delivery of RTL-to-GDSII implementation milestones, achievement of timing, power, area, and quality targets, and successful tape-out of ASIC/SoC designs. Performance will also be evaluated based on the ability to achieve signoff closure with minimal iterations, resolve complex implementation challenges, optimize design quality, and effectively lead engineering teams while delivering projects on schedule.