Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.
Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.
Job Summary:
We are seeking an experienced Senior Principal Engineer / Senior Manager – Physical Design Lead to lead the implementation and delivery of next-generation, high-performance SoC products built on advanced process technologies. This role will be responsible for driving the complete physical design execution of large-scale SoCs, from floorplanning through tape-out, while achieving aggressive performance, power, area, and schedule targets.
The ideal candidate will have a proven track record delivering complex 3nm and/or 5nm SoCs, with deep expertise in physical implementation of extremely high-speed designs incorporating large digital subsystems, high-speed SerDes interfaces, mixed-signal blocks, and advanced power management architectures.
Key Responsibilities:
- Lead the end-to-end physical design execution of large and complex SoCs from floorplanning through GDS signoff.
- Own implementation strategy, execution planning, risk management, and tape-out readiness.
- Drive floorplanning, power planning, placement, clock tree synthesis, routing, timing closure, signal integrity, IR/EM closure, and physical verification.
- Collaborate closely with architecture, RTL, verification, DFT, package, analog, and product engineering teams to optimize implementation quality and schedule.
- Define chip-level implementation methodologies and best practices to achieve challenging frequency, power, and area goals.
- Lead timing closure for complex multi-clock, high-frequency designs.
- Partner with package and system teams to optimize overall product performance and signal integrity.
- Drive implementation of advanced low-power architectures and ensure successful power-performance-area (PPA) optimization.
- Lead physical design reviews, signoff reviews, and tape-out milestones.
- Mentor senior physical design engineers and establish implementation excellence across the organization.
- Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline.
- 15-20+ years of experience in ASIC/SoC physical design.
- Proven experience leading physical design teams for large-scale, high-performance SoCs.
- Demonstrated success delivering advanced-node products, preferably at 3nm and/or 5nm technology nodes.
- Extensive experience across: Floor planning and Partitioning, Power Planning, Placement and Optimization, Clock Tree Synthesis (CTS), Routing and Congestion Analysis, Timing Closure, Signal Integrity Analysis, IR Drop and Electromigration (EM) Closure, Physical Verification and Signoff.
- Deep understanding of advanced-node implementation challenges including variation management, power integrity, and manufacturability.
- Strong knowledge of industry-standard physical design and signoff flows.
- Proven ability to lead large cross-functional teams and manage complex execution schedules.
Preferred Qualifications
Experience implementing:
- High-performance SoCs operating at aggressive frequency targets
- Large-scale switching and interconnect architectures
- Network-on-Chip (NoC) based designs
- High-bandwidth data movement fabrics
- Multi-billion transistor designs
- Experience integrating and closing timing on:
- High-speed SerDes subsystems
- Mixed-signal and analog IPs
- Advanced PHY technologies
- Memory controller and high-speed interface designs
- Strong understanding of package-level and system-level impacts on physical implementation and timing closure.
- Experience with advanced packaging and multi-die/chiplet architectures.
- Exposure to AI, HPC, networking, data-center, connectivity, or memory infrastructure products.
- Prior experience with high-performance switch fabrics, Ethernet switching, UALink, or similar interconnect technologies is desirable.
- Advanced Low-Power Expertise (Must Have)
- The successful candidate must have hands-on experience architecting and implementing advanced power optimization techniques in advanced-node SoCs, including:
- Multi-voltage and multi-power domain designs
- Dynamic Voltage and Frequency Scaling (DVFS)
- Power gating and retention strategies
- Clock gating methodologies
- Adaptive power management techniques
- UPF/CPF-based low-power implementation flows
- Leakage optimization and dynamic power reduction
- Low-power verification and signoff methodologies
- Power-aware physical design and implementation closure.
Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.
At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
Are you ready to join our team and shape the future with us?
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.
Skills Required
- Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline.
- 15-20+ years of experience in ASIC/SoC physical design.
- Proven experience leading physical design teams for large-scale, high-performance SoCs.
- Demonstrated success delivering advanced-node products, preferably at 3nm and/or 5nm technology nodes.
- Expertise in floorplanning and partitioning, power planning, placement and optimization, CTS, routing and congestion analysis, timing closure, and signal integrity analysis.
- Experience with IR drop and electromigration (EM) closure, physical verification and signoff.
- Deep understanding of advanced-node implementation challenges including variation management, power integrity, and manufacturability.
- Strong knowledge of industry-standard physical design and signoff flows.
- Proven ability to lead large cross-functional teams and manage complex execution schedules.
- Advanced low-power expertise (Must Have): multi-voltage and multi-power domain designs, DVFS, power gating, retention strategies, clock gating, adaptive power management.
- UPF/CPF-based low-power implementation flows and low-power verification and signoff methodologies.
- Leakage optimization and dynamic power reduction, power-aware physical design and implementation closure.
- Preferred: experience with high-performance SoCs at aggressive frequency targets, large-scale switching/interconnect architectures, NoC-based designs, high-bandwidth data movement fabrics, multi-billion transistor designs.
- Preferred: experience integrating and closing timing on high-speed SerDes subsystems, mixed-signal and analog IPs, advanced PHY technologies, and memory controller/high-speed interfaces.
- Preferred: strong understanding of package-level and system-level impacts, advanced packaging and multi-die/chiplet architectures, exposure to AI/HPC/networking/data-center products.
Renesas Electronics Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Renesas Electronics and has not been reviewed or approved by Renesas Electronics.
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Fair & Transparent Compensation — Feedback suggests pay is generally fair-to-good across many roles, with base pay aligned to prevailing market levels in multiple U.S. locations. Engineering and leadership tracks can be competitive on total compensation, reinforcing a sense that pay can meet market expectations in key job families.
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Healthcare Strength — Feedback suggests core medical, dental, and vision coverage is solid and well-regarded by employees. Day-one eligibility in U.S. roles is described, supporting confidence in access and continuity of care.
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Leave & Time Off Breadth — Feedback suggests PTO, paid holidays, sick time, and parental leave provide a comprehensive time-off framework. Company initiatives like Renesas Day and meeting-light Focus Fridays further support time away and balance.
Renesas Electronics Insights
What We Do
We're the world's leading semiconductor manufacturer. Our mission is to make our lives easier and a world that's safer, healthier, greener, and smarter.
