Physical Design Engineer

This role is for one of the Weekday's clients

Min Experience: 2+ years

Location: Bengaluru, Karnataka, India
JobType: full-time

We are seeking a talented Physical Design Engineer (PNR) to join our semiconductor engineering team. The ideal candidate will have hands-on experience in ASIC Physical Design, with expertise in Place & Route (PNR), floorplanning, power planning, and timing closure. You will play a key role in delivering high-performance, low-power, and area-efficient chip designs while collaborating closely with design, STA, and DFT teams throughout the implementation lifecycle.

This role offers the opportunity to work on advanced semiconductor technologies and contribute to the successful tape-out of complex ASIC designs.

• Perform end-to-end ASIC Physical Design (Place & Route) implementation for complex chip designs.
• Execute physical design activities including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and design closure.
• Optimize designs for timing, power, area, and congestion while ensuring implementation quality.
• Perform physical verification, design rule checks (DRC), and support engineering change orders (ECOs).
• Collaborate with RTL, STA, DFT, and verification teams to resolve implementation and timing-related issues.
• Analyze timing reports and implement fixes to achieve timing closure.
• Support low-power implementation and optimization methodologies.
• Work with physical design methodologies, automation, and best practices to improve implementation efficiency.
• Debug implementation issues and recommend design improvements to meet project goals.
• Contribute to continuous improvement of physical design flows and automation.

• 2–5 years of experience in ASIC Physical Design / Place & Route (PNR).
• Strong hands-on experience with Floorplanning.
• Expertise in Power Planning.
• Experience with Placement and physical optimization.
• Strong knowledge of Clock Tree Synthesis (CTS).
• Hands-on experience with Routing and routing optimization.
• Strong understanding of the complete ASIC physical design flow and timing closure.
• Experience using industry-standard EDA tools such as Cadence Innovus and/or Synopsys ICC2.
• Good understanding of physical verification, congestion analysis, and design optimization techniques.

• Experience with scripting using TCL, Perl, or Python.
• Exposure to EMIR (Electromigration and IR Drop) analysis.
• Familiarity with ECO implementation and low-power design methodologies.
• Understanding of advanced semiconductor technology nodes.
• Knowledge of DRC, LVS, and physical sign-off processes.

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
• 2–5 years of professional experience in ASIC Physical Design or Place & Route.
• Experience working on advanced-node semiconductor designs is an advantage.
• Familiarity with semiconductor design methodologies and industry-standard implementation flows.

• Strong analytical and debugging skills.
• Excellent problem-solving abilities with attention to detail.
• Good communication and collaboration skills.
• Ability to work effectively in cross-functional engineering teams.
• Self-motivated with the ability to manage multiple priorities in a fast-paced development environment.
• Strong commitment to quality, performance, and continuous learning.