Senior Physical Design Engineer

Posted 3 Hours Ago
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Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
Senior level
Artificial Intelligence • Cloud • Information Technology • Software
Creating world-changing technology that enriches the lives of every person on earth.
The Role
Execute end-to-end physical design for custom IP and SoC from RTL to GDS: synthesis, floorplanning, place-and-route, CTS, STA, signal integrity, power optimization, verification analysis, and methodology automation.
Summary Generated by Built In
Job Details:

Job Description: 

The Role and Impact

  • As a Physical Design Engineer, you will play a pivotal role in the implementation of custom IP and SoC designs, ensuring they are optimized for manufacturing and performance.
  • Your day-to-day responsibilities will involve executing the physical design flow from RTL to GDS, including synthesis, place and route, timing analysis, and verification.
  • By bringing your expertise to this critical part of chip design, you'll contribute to delivering high-performance, reliable, and innovative products that drive Intel's technological advancements.

Business group
You will be joining Intel's cutting-edge design engineering team, which focuses on creating world-class solutions for silicon design and manufacturing. The group collaborates across domains to develop advanced methodologies that support Intel's mission to produce high-performing, energy-efficient, and scalable products. With a culture rooted in innovation and teamwork, the group plays a key role in shaping Intel's leadership in semiconductor technology.
Key Responsibilities
- Conduct end-to-end physical design implementation of custom IP and SoC designs from RTL to GDS.
- Execute synthesis, floor planning, place and route, and clock tree synthesis to meet design specifications.
- Perform static timing analysis, noise glitch/signal integrity analysis, and power distribution optimization.
- Analyze verification results, including equivalence checks, power integrity, reliability checks, and timing closure, and make recommendations for resolving violations.
- Collaborate with cross-functional teams to optimize design parameters such as power, area, and frequency.
- Contribute to the development and enhancement of physical design methodologies, flows, and automation for improved efficiency and scalability.

Qualifications:

Minimum Qualifications
- Bachelor's degree in a specialized field such as Electrical Engineering, Computer Engineering, or similar with 8+ years of hands-on experience in physical design OR Master's degree with 6+ years of experience OR PhD with 4+ years of experience.
- Proficiency in key physical design tools and flows, including synthesis, FC / Innovus place and route, static timing analysis, and verification methodologies.
- Expertise in design optimization techniques, power planning, clock tree synthesis, and low-power design methodologies.
- Demonstrated ability to handle EDA tools with the latest AI/ML capabilities for design automation.
- Strong scripting skills for flow automation and process efficiency (e.g., Python, Perl, TCL).
Preferred Qualifications
- Experience in DFT physical design implementation and formal verification flows.
- Knowledge of advanced floor planning techniques and macro placement.
- Strong problem-solving ability and collaborative mindset.
- Commitment to driving innovation in design methodologies and process improvement.

- Exposure or Usage of Agentic AI & ML tools
Your expertise and skills are essential to Intel's success in delivering groundbreaking technology. We invite you to be part of a team that thrives on innovation, collaboration, and making a meaningful impact in the semiconductor industry.

          

Job Type:Experienced Hire

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Skills Required

  • Bachelor's degree in Electrical/Computer Engineering or similar with 8+ years, or Master's with 6+ years, or PhD with 4+ years
  • Proficiency in physical design tools and flows including synthesis, place and route (Fusion Compiler/Innovus), static timing analysis, and verification methodologies
  • Expertise in design optimization, power planning, clock tree synthesis, and low-power design methodologies
  • Experience using EDA tools with AI/ML capabilities for design automation
  • Strong scripting skills for flow automation (Python, Perl, TCL)
  • Experience in DFT physical design implementation and formal verification flows
  • Knowledge of advanced floor planning techniques and macro placement
  • Exposure or usage of agentic AI & ML tools
  • Strong problem-solving ability, collaborative mindset, and commitment to process improvement

Intel Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.

  • Parental & Family Support Family-building and caregiving supports are extensive, including fertility coverage, adoption assistance, paid parental leave, childcare and elder care resources, and a structured reintegration for new parents. These benefits are positioned as best-in-class elements of the package.
  • Leave & Time Off Breadth Time off includes generous PTO, a paid sabbatical after extended tenure, and multiple leave types such as family, medical, bereavement, and military. This breadth enables employees to disconnect, recharge, and manage life events.
  • Retirement Support Long-term savings are bolstered by a competitive 401(k) match and access to deferred compensation for eligible levels, alongside stock purchase opportunities. These programs are highlighted as strong tools for financial security.

Intel Insights

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The Company
HQ: Santa Clara, CA
75,000 Employees
Year Founded: 1968

What We Do

Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone.

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