The Opportunity
For nearly a decade, Intel's Neuromorphic Computing Lab-together with a global ecosystem of 250+ research groups-has explored architectures, algorithms, and software inspired by the brain's extraordinary efficiency, scalability, and adaptability. Our Loihi series of research chips pioneered event-driven, sparse, and massively parallel neuro-inspired processing, fueling over 100 peer-reviewed publications that validate the promise of this novel approach.
Now, we're entering an exciting new chapter: transforming these breakthroughs into real-world products that will power the coming era of physical AI systems-beyond the reach of GPUs and mainstream AI accelerators.
If you are passionate about pushing the boundaries of computing, from transistor-level innovation to software abstractions, join us. Help define the next wave of AI technology that harnesses the proven advantages of Intel's neuromorphic computing technology with the versatility demanded by modern AI workloads.
Position Overview
We are seeking an experienced design automation engineer passionate about driving innovation at the intersection between emerging semiconductor technology, physical AI and novel computing paradigms. Loihi's silicon design flow is unique in the industry combining high-performance asynchronous design methods with standard EDA tools for silicon implementation. You will help pioneer the tool flows and automation methods required to bring these novel designs from concept to silicon, developing new capabilities spanning front-end design, physical implementation, verification, and FPGA-based emulation. Candidates should be familiar with the entire silicon design lifecycle and adapt to the requirements of our custom flow. A strong software background and an openness to learning new technologies and methodologies, such as asynchronous design, is essential. Experience with the latest AI-driven automation, agentic engineering assistants, and generative AI development tools is expected and will be a key contributor to success in this role.
Responsibilities
• Enhance and maintain Loihi's asynchronous EDA tool flow by implementing design automation algorithms, software tools, utilities, and regression tests.
• Support RTL designers, verification engineers and physical design engineers by providing automated solutions to achieve product quality and target KPIs.
• Enable early SW development by setting up a scalable framework mapping silicon designs in simulation and emulation.
• Write custom scripts to manipulate synthesis and physical design tools for low power/high performance custom designs.
Minimum qualifications
• Bachelors and 4+ years OR Masters and 2+ years of experience in developing and deploying production quality tools, flows and methods for silicon design.
• 4+ years of experience in developing and maintaining the entire ASIC tool suite. E.g. synthesis, place and route, ATPG, FEV, RV, STA, LVS/DRC.
• 4+ years of experience with scripting languages such as Perl, TCL, Python, etc.
• 2+ years of experience in delivering multiple silicon tape-outs.
Preferred qualifications
• Strong System-Verilog/System-C/Object Oriented Programming background.
• Experience with large scale FPGA platforms like HAPS and/or emulation frameworks like ZeBu.
• 1+ year of experience using AI tools for setting up tool flows, debugging and improving overall productivity.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, AustinPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor’s degree and 4+ years, or Master’s degree and 2+ years, developing and deploying production-quality tools, flows, and methods for silicon design
- 4+ years of experience developing and maintaining the full ASIC tool suite, including synthesis, place and route, ATPG, FEV, RV, STA, LVS, and DRC
- 4+ years of experience with scripting languages such as Perl, Tcl, or Python
- 2+ years of experience delivering multiple silicon tape-outs
- Strong SystemVerilog, SystemC, and object-oriented programming background
- Experience with large-scale FPGA platforms such as HAPS or emulation frameworks such as ZeBu
- 1+ year of experience using AI tools to establish tool flows, debug, and improve productivity
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
-
Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
-
Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
-
Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
Intel Insights
What We Do
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone.
