Jobs at Tensordyne

Develop system-level platform software for high-performance AI inference systems, including firmware, bootloaders, BSPs, device drivers, Linux kernel modules, debugging tools, and tests. Support hardware and silicon bring-up, validation, performance and power optimization, and hardware/software co-design. The role requires close collaboration across software, hardware, silicon, and validation teams, with occasional travel to partners, customers, or manufacturing sites.

Develop system-level software, firmware, tools, and tests for high-performance AI inference platforms. Responsibilities include Linux kernel and driver development, bootloader and BSP work, hardware and silicon bring-up, debugging, profiling, performance and power optimization, and low-level interface integration. The engineer will collaborate with hardware, validation, and silicon teams to deliver production-quality software and support platform deployment in data centers.

Design and develop distributed cloud services in Rust, maintain in-house Rust software, build generative AI APIs, and collaborate across teams on technical specifications and implementation. The role also involves coordinating agent teams and applying asynchronous Rust design patterns, networking concepts, HTTP, Kubernetes, and related cloud technologies.

Maintain and enhance Tensordyne’s internal developer platform, including CI pipelines, cloud development and build environments, Rust-based developer services, ML workflow orchestration, and agentic platforms. Manage and optimize GCP infrastructure while supporting scalable developer workflows and MLOps capabilities. The role involves infrastructure as code, Kubernetes, Git, Python, Flyte, and modern software engineering practices.

Build and optimize a backend compiler that transforms AI workloads into microcode for custom inference silicon. Responsibilities include lowering, instruction scheduling, register and resource allocation, memory hierarchy optimization, tiling, fusion, software pipelining, cost modeling, dynamic-shape support, and compiler interfaces for engineers and AI agents. The role also involves co-designing compiler, runtime, kernels, ISA, and silicon while improving performance against real hardware.

Lead ASIC front-end physical design and workflow development for generative AI inference chips. Optimize block-level and full-chip implementation using Cadence and Synopsys tools, including synthesis, formal checks, power analysis, and static timing analysis. Support backend design activities involving clock trees, routing, DRC, LVS, metal fill, and artwork release. Collaborate with global ASIC, design, and verification teams while developing scalable, high-performance EDA workflows.

Lead full-chip and block-level ASIC static timing analysis, timing closure, signoff, and workflow development for generative AI accelerator products. Develop hierarchical constraints and SDCs for high-speed interfaces and multi-clock domains, analyze clocking and routing issues, generate timing ECOs, and improve Cadence/Synopsys-based physical design flows. Collaborate with global ASIC design and verification teams as a hands-on technical leader.

Develop and maintain functional models for an AI inference accelerator. Implement and test architectural features, investigate discrepancies between models and hardware, validate models against architecture specifications and RTL, improve modeling techniques, and maintain the codebase while collaborating across architecture, hardware, and software teams.

Leads strategic technical engagements for an AI inference platform from architecture evaluation through benchmarking, model enablement, deployment, and production rollout. Builds and manages a high-performing solutions engineering team, guides customer evaluations and deployments, translates customer requirements into product priorities, and develops scalable technical go-to-market assets. Requires deep expertise in AI inference, accelerator architecture, distributed systems, serving frameworks, performance optimization, and customer-facing technical leadership.

Own full-cycle technical recruiting across ASIC, semiconductor, hardware, software, AI infrastructure, operations, sales, product, finance, HR, and leadership roles. Partner with hiring managers, develop sourcing and talent-mapping strategies, screen and close candidates, provide market intelligence, and build pipelines for current and future workforce needs.

Build simulation-based performance models and trace-replay tools for generative AI inference across accelerators, fabrics, racks, pods, and clusters. Model distributed execution, communication, networking, and serving strategies; run hardware calibration experiments; compare predictions with measurements; perform design-space analyses; and provide performance projections for architecture, product, and customer decisions.

Designs high-performance AI ASICs, including microarchitecture specifications, complex RTL, CPU and third-party IP integration, and low-power implementations. Collaborates with physical design and verification teams on timing, power, coverage closure, and implementation issues. Performs diagnostic and post-silicon validation and supports software bring-up in the lab. The role also contributes to specification reviews, vendor engagement, and exploration of accelerator architectures for AI workloads.

Lead ASIC verification for next-gen processors in AI inference. Oversee full verification cycle, mentor engineers, and establish methodologies.

The role involves leading the development of AI inference compute products, engaging with partners and customers, and managing product strategies and performance metrics.

The Sr. Staff Hardware Design Engineer will oversee hardware system engineering for AI products, handle schematic capture and PCB design, and coordinate with teams for product compliance and validation.

The Hardware Design Engineer will oversee hardware system development including schematics, PCB layout, and component selection while collaborating with various teams for product testing and validation.

Responsible for Design Verification Testing and sustaining of new hardware products, including creating test plans, debugging, and ensuring performance specifications are met.

Lead pre-silicon ASIC verification for a multi-million-gate SoC: plan verification, build SystemVerilog/UVM testbenches, run constrained-random tests and coverage, debug functional/performance issues, drive signoff, mentor engineers, and perform post-silicon lab validation.

The Staff Hardware Design Engineer will lead hardware system development for AI products, focusing on schematic design, PCB layout, compliance, and cross-team collaboration.

Design, build, and optimize multi-hop data center fabrics for large-scale AI inference. Work across userspace, kernel, drivers, ASIC SDKs, firmware, and optics to tune latency, bandwidth, and reliability. Lead fabric bring-up, telemetry, automation, validation, and operational best practices while mentoring teammates and partnering with hardware, platform, and manufacturing teams.