Jobs at Tensordyne

Lead ASIC front-end physical design and workflow development for generative AI inference chips. Optimize block-level and full-chip implementation using Cadence and Synopsys tools, including synthesis, formal checks, power analysis, and static timing analysis. Support backend design activities involving clock trees, routing, DRC, LVS, metal fill, and artwork release. Collaborate with global ASIC, design, and verification teams while developing scalable, high-performance EDA workflows.

Own customer model deployment and optimization on Tensordyne’s AI inference platform. Profile and benchmark workloads, enable models, validate quality, diagnose performance across software and hardware, support customer PoCs and deployments, and translate recurring technical learnings into tooling, documentation, benchmarks, and product improvements. Collaborate across compiler, runtime, kernel, systems, Product, Sales, and customer teams.

Lead full-chip and block-level ASIC static timing analysis, timing closure, signoff, and workflow development for generative AI accelerator products. Develop hierarchical constraints and SDCs for high-speed interfaces and multi-clock domains, analyze clocking and routing issues, generate timing ECOs, and improve Cadence/Synopsys-based physical design flows. Collaborate with global ASIC design and verification teams as a hands-on technical leader.

Develop and maintain functional models for an AI inference accelerator. Implement and test architectural features, investigate discrepancies between models and hardware, validate models against architecture specifications and RTL, improve modeling techniques, and maintain the codebase while collaborating across architecture, hardware, and software teams.

Leads strategic technical engagements for an AI inference platform from architecture evaluation through benchmarking, model enablement, deployment, and production rollout. Builds and manages a high-performing solutions engineering team, guides customer evaluations and deployments, translates customer requirements into product priorities, and develops scalable technical go-to-market assets. Requires deep expertise in AI inference, accelerator architecture, distributed systems, serving frameworks, performance optimization, and customer-facing technical leadership.

Own full-cycle technical recruiting across ASIC, semiconductor, hardware, software, AI infrastructure, operations, sales, product, finance, HR, and leadership roles. Partner with hiring managers, develop sourcing and talent-mapping strategies, screen and close candidates, provide market intelligence, and build pipelines for current and future workforce needs.

Build simulation-based performance models and trace-replay tools for generative AI inference across accelerators, fabrics, racks, pods, and clusters. Model distributed execution, communication, networking, and serving strategies; run hardware calibration experiments; compare predictions with measurements; perform design-space analyses; and provide performance projections for architecture, product, and customer decisions.

Designs high-performance AI ASICs, including microarchitecture specifications, complex RTL, CPU and third-party IP integration, and low-power implementations. Collaborates with physical design and verification teams on timing, power, coverage closure, and implementation issues. Performs diagnostic and post-silicon validation and supports software bring-up in the lab. The role also contributes to specification reviews, vendor engagement, and exploration of accelerator architectures for AI workloads.

Lead design and development of system-level services, diagnostics, and tooling for an AI inference platform. Support board/firmware bring-up, kernel and driver development, hardware/software co-design, manufacturing test integration, and system-level performance and power optimization. Collaborate with silicon, hardware, and manufacturing teams to debug and validate platform software.

Lead ASIC verification for next-gen processors in AI inference. Oversee full verification cycle, mentor engineers, and establish methodologies.

The role involves leading the development of AI inference compute products, engaging with partners and customers, and managing product strategies and performance metrics.

The Sr. Staff Hardware Design Engineer will oversee hardware system engineering for AI products, handle schematic capture and PCB design, and coordinate with teams for product compliance and validation.

Drive adoption of AI inference platform across large enterprises, own sales cycle, lead technical evaluations, engage executive stakeholders, and shape GTM strategy.

The Hardware Design Engineer will oversee hardware system development including schematics, PCB layout, and component selection while collaborating with various teams for product testing and validation.

Responsible for Design Verification Testing and sustaining of new hardware products, including creating test plans, debugging, and ensuring performance specifications are met.

Lead pre-silicon ASIC verification for a multi-million-gate SoC: plan verification, build SystemVerilog/UVM testbenches, run constrained-random tests and coverage, debug functional/performance issues, drive signoff, mentor engineers, and perform post-silicon lab validation.

The Staff Hardware Design Engineer will lead hardware system development for AI products, focusing on schematic design, PCB layout, compliance, and cross-team collaboration.

Design, build, and optimize multi-hop data center fabrics for large-scale AI inference. Work across userspace, kernel, drivers, ASIC SDKs, firmware, and optics to tune latency, bandwidth, and reliability. Lead fabric bring-up, telemetry, automation, validation, and operational best practices while mentoring teammates and partnering with hardware, platform, and manufacturing teams.

Lead ASIC architecture definition and design for AI processors, focusing on high-performance compute and generative AI solutions. Oversee design processes and mentor teams, ensuring functionality and performance standards.

Design and implement RTL microarchitecture for a high-performance, low-power CNN accelerator ASIC. Integrate CPU and 3rd-party SoC IP, collaborate on timing closure and power optimization, support verification and post-silicon bring-up, and assist software/hardware validation in lab.