Jobs at Tensordyne

Lead design and development of system-level services, diagnostics, and tooling for an AI inference platform. Support board/firmware bring-up, kernel and driver development, hardware/software co-design, manufacturing test integration, and system-level performance and power optimization. Collaborate with silicon, hardware, and manufacturing teams to debug and validate platform software.

Lead ASIC verification for next-gen processors in AI inference. Oversee full verification cycle, mentor engineers, and establish methodologies.

The Sr. Staff Hardware Design Engineer will oversee hardware system engineering for AI products, handle schematic capture and PCB design, and coordinate with teams for product compliance and validation.

The Hardware Design Engineer will oversee hardware system development including schematics, PCB layout, and component selection while collaborating with various teams for product testing and validation.

Responsible for Design Verification Testing and sustaining of new hardware products, including creating test plans, debugging, and ensuring performance specifications are met.

Lead pre-silicon ASIC verification for a multi-million-gate SoC: plan verification, build SystemVerilog/UVM testbenches, run constrained-random tests and coverage, debug functional/performance issues, drive signoff, mentor engineers, and perform post-silicon lab validation.

The Staff Hardware Design Engineer will lead hardware system development for AI products, focusing on schematic design, PCB layout, compliance, and cross-team collaboration.

Drive adoption of AI inference platform across large enterprises, own sales cycle, lead technical evaluations, engage executive stakeholders, and shape GTM strategy.

Develop and implement manufacturing test solutions for high-performance AI servers, focusing on automated testing, collaboration with teams, and debug analysis.

Lead EDA tools and DevOps systems for ASIC chip design at Tensordyne, focusing on enhancing EDA workflows and technical support for a global engineering team.

Design, build, and optimize multi-hop data center fabrics for large-scale AI inference. Work across userspace, kernel, drivers, ASIC SDKs, firmware, and optics to tune latency, bandwidth, and reliability. Lead fabric bring-up, telemetry, automation, validation, and operational best practices while mentoring teammates and partnering with hardware, platform, and manufacturing teams.

Lead ASIC architecture definition and design for AI processors, focusing on high-performance compute and generative AI solutions. Oversee design processes and mentor teams, ensuring functionality and performance standards.