Teams at Tensordyne

Lead ASIC front-end physical design and workflow development for generative AI inference chips. Optimize block-level and full-chip implementation using Cadence and Synopsys tools, including synthesis, formal checks, power analysis, and static timing analysis. Support backend design activities involving clock trees, routing, DRC, LVS, metal fill, and artwork release. Collaborate with global ASIC, design, and verification teams while developing scalable, high-performance EDA workflows.

Own customer model deployment and optimization on Tensordyne’s AI inference platform. Profile and benchmark workloads, enable models, validate quality, diagnose performance across software and hardware, support customer PoCs and deployments, and translate recurring technical learnings into tooling, documentation, benchmarks, and product improvements. Collaborate across compiler, runtime, kernel, systems, Product, Sales, and customer teams.

Lead full-chip and block-level ASIC static timing analysis, timing closure, signoff, and workflow development for generative AI accelerator products. Develop hierarchical constraints and SDCs for high-speed interfaces and multi-clock domains, analyze clocking and routing issues, generate timing ECOs, and improve Cadence/Synopsys-based physical design flows. Collaborate with global ASIC design and verification teams as a hands-on technical leader.