Jobs at SiTime

Lead analog mixed-signal circuit and chip development for precision timing products. Define architectures, perform transistor-level design and simulations, supervise designers and layout, run post-layout extraction and Monte Carlo analysis, collaborate across teams for DFT/DFM and silicon bring-up, and drive validation, characterization, and production release.

Design and verify analog and mixed-signal circuits to meet specifications, contribute to architecture and chip integration, collaborate on layout and DFT/DFM, support bring-up, evaluation and characterization, and work cross-functionally with product, test, and application teams.

Lead chip-level planning and perform block- and leaf-cell custom layouts for CMOS/BiCMOS circuits. Drive floorplanning, power/shielding, verify DRC/LVS/ERC, support chip integration and tape-out, train junior and offshore layout engineers, and develop cross-site layout methodologies and processes.

Design and verify analog and mixed-signal circuits (PLLs, ADCs, regulators, oscillators) from architecture through layout, participate in chip bring-up, collaborate with cross-functional teams, and document and review assigned blocks.

Provide timely responses to customer inquiries on product specs, pricing, lead times, quality, and basic technical questions. Use CRM and ERP systems to investigate and resolve shipment, RMA, and billing issues; escalate to engineering or quality as needed. Track and document issues, perform data mining, and collaborate across departments to support customer needs.

Lead strategic engagement and sales with ODMs and multinational customers in AI, networking, and communications. Drive design wins, manage accounts, develop pipeline and forecasts, collaborate cross-functionally, and influence the server value chain for long-term revenue growth.

Lead Asia regional accounting, financial reporting, and internal controls across multiple jurisdictions. Oversee close, consolidation, statutory filings, SOX compliance, audits, ERP improvements (Oracle), and provide financial insights, governance, and process standardization while partnering with regional and corporate leadership.

Design and verify analog and mixed-signal circuits for precision timing products. Contribute to architecture, perform schematic and post-layout verification, collaborate on layout, participate in chip bring-up and characterization, and work cross-functionally with Product, Test, and Applications teams.

Lead and execute reliability qualification testing for products at the Taiwan office. Manage technicians and day-to-day qual activities, coordinate vendors, collaborate with NPI and infrastructure teams to source hardware/software, perform first-order data analysis and initial failure analysis, and report FACA/errors while partnering with cross-functional teams including the US office.

Lead and expand strategic semiconductor partnerships in China, drive design-ins and platform/system-level design wins, manage full engagement cycle from reference design to ODM/CM/OEM, influence joint product roadmaps, and collaborate cross-functionally to convert design activity into revenue.

The Time Synchronization System Architect will develop technical relationships with key customers, drive architectural discussions, influence SiTime's roadmap, and advocate technical expertise for design wins in data centers and networking markets.

Design and verify analog and mixed-signal circuits for precision timing products. Contribute to architecture, perform schematic and post-layout simulations, work with layout, participate in chip bring-up and characterization, and collaborate cross-functionally on owned circuit blocks.

Design and verify analog and mixed-signal circuits to meet specs; contribute to architecture and chip integration; run schematic and post-layout simulations; coordinate layout and DFT/DFM; document designs and lead reviews; support chip bring-up, characterization, and cross-functional issue resolution.

Coordinate recruiting operations and interview scheduling, maintain ATS accuracy, support offer processes and recruiting analytics. Proactively source and engage technical and early-career candidates, screen resumes, build pipelines, track sourcing metrics, and partner with recruiters and hiring managers to improve processes and candidate experience.

Lead chip-level planning and perform block- and leaf-cell custom layouts for CMOS/BiCMOS. Drive schematic-driven layout, floorplanning, power planning, DRC/LVS/ERC verification, chip integration and tape-out. Mentor junior and offshore layout engineers, develop cross-site methodologies, and improve layout processes and automation.

Lead design, development, and qualification of custom semiconductor packages (QFN, WLCSP, substrate, ceramic, MCM) for MEMS/CMOS timing products. Manage DoEs, prototype and test with OSATs, ensure performance, reliability and quality, and lead troubleshooting and release-to-production activities.

Lead specification, design, development, and qualification of custom semiconductor packaging (QFN, WLCSP, substrate, ceramic, multi-chip). Manage package design, DoEs, OSAT development/prototyping, ensure performance/reliability/quality, and lead troubleshooting and release-to-production activities.

Lead specification, design, development, and qualification of custom semiconductor packaging (QFN, WLCSP, substrate, multi-chip) for MEMS/CMOS products. Manage DoEs, prototype/test activities with OSATs, ensure performance, reliability, quality, and lead troubleshooting to release packages to production.

Lead chip-level planning and perform block- and leaf-cell custom layouts for CMOS/BiCMOS circuits. Drive schematic-driven layouts, floorplanning, power and shielding, DRC/LVS/ERC verification, chip integration and tape-out. Mentor junior/offshore layout engineers and help establish layout methodologies, processes, and automation.

The SEC Reporting, SOX & ESG Compliance Manager prepares SEC filings, manages SOX compliance, and coordinates ESG reporting, collaborating across functions for process improvement.