Jobs at SiTime

Lead chip top-level planning and perform block- and cell-level custom layouts for CMOS/BiCMOS. Drive floorplanning, power distribution, shielding, verification (DRC/LVS/ERC), chip integration and tape-out. Mentor junior and offshore layout engineers and help establish cross-site layout methodologies and processes.

Provide timely responses to customer inquiries on product specs, pricing, lead times, quality, and basic technical questions. Use CRM and ERP systems to investigate and resolve shipment, RMA, and billing issues; escalate to engineering or quality as needed. Track and document issues, perform data mining, and collaborate across departments to support customer needs.

Lead strategic engagement and sales with ODMs and multinational customers in AI, networking, and communications. Drive design wins, manage accounts, develop pipeline and forecasts, collaborate cross-functionally, and influence the server value chain for long-term revenue growth.

Lead Asia regional accounting, financial reporting, and internal controls across multiple jurisdictions. Oversee close, consolidation, statutory filings, SOX compliance, audits, ERP improvements (Oracle), and provide financial insights, governance, and process standardization while partnering with regional and corporate leadership.

The Time Synchronization System Architect will develop technical relationships with key customers, drive architectural discussions, influence SiTime's roadmap, and advocate technical expertise for design wins in data centers and networking markets.

Lead and expand strategic semiconductor partnerships in China, drive design-ins and platform/system-level design wins, manage full engagement cycle from reference design to ODM/CM/OEM, influence joint product roadmaps, and collaborate cross-functionally to convert design activity into revenue.

Coordinate recruiting operations and interview scheduling, maintain ATS accuracy, support offer processes and recruiting analytics. Proactively source and engage technical and early-career candidates, screen resumes, build pipelines, track sourcing metrics, and partner with recruiters and hiring managers to improve processes and candidate experience.

Lead chip-level planning and perform block- and leaf-cell custom layouts for CMOS/BiCMOS. Drive schematic-driven layout, floorplanning, power planning, DRC/LVS/ERC verification, chip integration and tape-out. Mentor junior and offshore layout engineers, develop cross-site methodologies, and improve layout processes and automation.

Lead design, development, and qualification of custom semiconductor packages (QFN, WLCSP, substrate, ceramic, MCM) for MEMS/CMOS timing products. Manage DoEs, prototype and test with OSATs, ensure performance, reliability and quality, and lead troubleshooting and release-to-production activities.

Lead specification, design, development, and qualification of custom semiconductor packaging (QFN, WLCSP, substrate, ceramic, multi-chip). Manage package design, DoEs, OSAT development/prototyping, ensure performance/reliability/quality, and lead troubleshooting and release-to-production activities.

Lead specification, design, development, and qualification of custom semiconductor packaging (QFN, WLCSP, substrate, multi-chip) for MEMS/CMOS products. Manage DoEs, prototype/test activities with OSATs, ensure performance, reliability, quality, and lead troubleshooting to release packages to production.

Lead chip-level planning and perform block- and leaf-cell custom layouts for CMOS/BiCMOS circuits. Drive schematic-driven layouts, floorplanning, power and shielding, DRC/LVS/ERC verification, chip integration and tape-out. Mentor junior/offshore layout engineers and help establish layout methodologies, processes, and automation.

The SEC Reporting, SOX & ESG Compliance Manager prepares SEC filings, manages SOX compliance, and coordinates ESG reporting, collaborating across functions for process improvement.

The Senior Test Engineer develops hardware and software test solutions for precision timing devices, focusing on ATE development, board-level design, and algorithm implementation for production testing.

The Sr. Engineer, MEMS will design, validate, and improve MEMS devices, collaborate with teams, and manage processes to enhance MEMS manufacturing.

The Senior Test Development Engineer develops hardware and software test solutions for precision timing devices, ensuring quality and efficiency from product development to production launch.

The MEMS Engineer II will characterize MEMS resonators, analyze measurement data, design wafer-level tests, and support project goals.

The Sr. Sales Manager will engage customers, manage sales activities, lead technical discussions, and drive design wins in the AI and semiconductor sectors.

The Account Manager drives sales growth in the DACH region, manages key accounts, presents products, and collaborates with engineering to meet customer needs.

Lead the design and development of FPGA-based platforms for testing MEMS timing products, ensuring alignment across hardware and software. Provide technical leadership and mentorship while overseeing the full FPGA lifecycle.