Jobs at SiTime

Lead and expand strategic semiconductor partnerships in China, drive design-ins and platform/system-level design wins, manage full engagement cycle from reference design to ODM/CM/OEM, influence joint product roadmaps, and collaborate cross-functionally to convert design activity into revenue.

Lead and execute reliability qualification testing for products at the Taiwan office. Manage technicians and day-to-day qual activities, coordinate vendors, collaborate with NPI and infrastructure teams to source hardware/software, perform first-order data analysis and initial failure analysis, and report FACA/errors while partnering with cross-functional teams including the US office.

Design and verify analog and mixed-signal circuits for precision timing products. Contribute to architecture, perform schematic and post-layout verification, collaborate on layout, participate in chip bring-up and characterization, and work cross-functionally with Product, Test, and Applications teams.

Serve as primary HR contact for APAC, managing onboarding, employee relations intake, HR operations, benefits administration, compliance, recruiting coordination, engagement programs, and partnering with global HR on talent and compensation initiatives.

Design and verify analog and mixed-signal circuits for precision timing products. Contribute to architecture, perform schematic and post-layout simulations, work with layout, participate in chip bring-up and characterization, and collaborate cross-functionally on owned circuit blocks.

Coordinate recruiting operations and interview scheduling, maintain ATS accuracy, support offer processes and recruiting analytics. Proactively source and engage technical and early-career candidates, screen resumes, build pipelines, track sourcing metrics, and partner with recruiters and hiring managers to improve processes and candidate experience.

Coordinate recruiting operations and scheduling, maintain ATS accuracy, and support offer coordination. Proactively source technical and early-career talent, engage passive candidates, screen resumes, and build pipelines. Partner with recruiters and hiring managers on sourcing strategy, track pipeline and sourcing metrics, and support recruiting analytics, process improvements, and ad hoc talent projects to improve time-to-fill and candidate experience.

Lead development and standardization of SOPs, work instructions, and operational documentation across manufacturing, operations, quality, test, and supply chain. Capture SME knowledge, create process maps, training materials, and enforce document control/versioning. Use AI tools to improve documentation quality and support audit, process improvement, and operational readiness over a 6-month contract.

Coordinate recruiting operations and interview logistics, maintain ATS accuracy, and support offer coordination. Proactively source and engage technical and early-career candidates, screen resumes, build pipelines, track sourcing metrics, and partner with hiring managers to improve recruiting processes and analytics.

Design and implement digital logic for MEMS/CMOS timing products: create micro-architecture and RTL (Verilog/SystemVerilog), develop testbenches and SVA, define timing constraints, run synthesis/STA, fix timing, collaborate across teams, and support post-silicon bring-up and validation.

Lead transition of new MEMS-based semiconductor products to high-volume manufacturing. Develop and document manufacturing and test process flows, bring up OSAT, support early sampling and low-volume manufacturing, perform process capability and test data analysis, run initial failure analysis, report production capacity, and create RTP/documentation templates with cross-functional teams.

Lead specification, design, development, and qualification of custom semiconductor packaging (QFN, WLCSP, substrate, ceramic, multi-chip). Manage package design, DoEs, OSAT development/prototyping, ensure performance/reliability/quality, and lead troubleshooting and release-to-production activities.

Design and simulate high-performance CMOS analog and custom digital circuits for precision timing products. Prepare design reviews and documentation, collaborate with layout, digital, system, and validation teams, and test, debug, and characterize prototypes in the lab.

Provide technical leadership and hands-on analog/mixed-signal CMOS circuit design for high-performance timing products. Design and develop PLLs, VCOs, phase detectors, and charge pumps; support prototyping, lab characterization, and post-layout verification; collaborate with cross-functional and remote teams; mentor junior designers and drive product development through production release.

Lead analog/mixed-signal circuit design for high-performance timing products, from concept through production. Provide hands-on design of PLLs and related blocks, support prototype testing and lab characterization, collaborate with cross-functional and remote teams, and mentor junior designers.

The SEC Reporting, SOX & ESG Compliance Manager prepares SEC filings, manages SOX compliance, and coordinates ESG reporting, collaborating across functions for process improvement.

The Time Synchronization System Architect will develop technical relationships with key customers, drive architectural discussions, influence SiTime's roadmap, and advocate technical expertise for design wins in data centers and networking markets.

Lead block-level chip planning and perform custom analog and full-custom digital layout for CMOS/BiCMOS circuits. Develop floorplans, power distribution, shielding, and device-matching layouts; execute schematic-driven layouts, verify DRC/LVS/ERC, support chip integration and tape-out, mentor junior/offshore engineers, and improve layout processes and workflows.

Manage an assigned US territory of long-tail accounts to drive customer expansion and revenue growth. Use digital marketing and distributor channels to scale engagement, qualify opportunities, engage engineering and sourcing teams, advance deals toward design-in and wins, maintain pipeline and forecasts, and coordinate with distribution partners for demand generation and opportunity tracking.

Lead and perform custom analog and full‑custom digital layout at chip and block levels using Cadence Virtuoso; develop floorplans, power distribution, device‑matching, verify DRC/LVS/ERC, support tape‑out, mentor junior and offshore layout engineers, and standardize layout methodologies and processes.