Jobs at SiTime

Lead transition of new MEMS-based semiconductor products to high-volume manufacturing. Develop and document manufacturing and test process flows, bring up OSAT, support early sampling and low-volume manufacturing, perform process capability and test data analysis, run initial failure analysis, report production capacity, and create RTP/documentation templates with cross-functional teams.

Seeking a senior customer engineer to develop technical relationships, drive design solutions, and support customers in the datacenter, AI, and telecom sectors.

The Director, Infrastructure Hardware will lead the development and delivery of hardware platforms, manage cross-functional teams, and ensure operational excellence while improving processes and performance.

Lead specification, design, development, and qualification of custom semiconductor packaging (QFN, WLCSP, substrate, ceramic, multi-chip). Manage package design, DoEs, OSAT development/prototyping, ensure performance/reliability/quality, and lead troubleshooting and release-to-production activities.

Provide technical leadership and hands-on analog/mixed-signal CMOS circuit design for high-performance timing products. Design and develop PLLs, VCOs, phase detectors, and charge pumps; support prototyping, lab characterization, and post-layout verification; collaborate with cross-functional and remote teams; mentor junior designers and drive product development through production release.

Lead analog/mixed-signal circuit design for high-performance timing products, from concept through production. Provide hands-on design of PLLs and related blocks, support prototype testing and lab characterization, collaborate with cross-functional and remote teams, and mentor junior designers.

Design and simulate high-performance CMOS analog and custom digital circuits for precision timing products. Prepare design reviews and documentation, collaborate with layout, digital, system, and validation teams, and test, debug, and characterize prototypes in the lab.

Lead development of automated test solutions for mixed-signal semiconductor timing devices from product kickoff through high-volume production. Define test flows, develop C++ test software, design and validate test hardware, debug and optimize programs, perform correlation and characterization studies, and support qualification and release activities. Collaborate with engineering, manufacturing, quality, equipment, and OSAT teams while mentoring junior staff.

Develop ATE hardware and software test solutions for precision timing devices from product development through high-volume production. Responsibilities include defining test plans and flows, developing C++ test software, designing and validating DUT boards and fixtures, debugging and correlating test systems, characterizing performance, supporting NPI and production releases, documenting changes, and collaborating with engineering, manufacturing, quality, equipment, and OSAT teams.

Coordinates employee experience programs, onboarding, company meetings, events, learning and development initiatives, and HR administrative processes. Manages logistics, communications, scheduling, materials, participation tracking, and follow-up activities while supporting HR projects and collaborating with employees, leaders, and cross-functional teams. The role requires strong organization, communication, discretion, multitasking, and adaptability in a fast-paced environment.

The Time Synchronization System Architect will develop technical relationships with key customers, drive architectural discussions, influence SiTime's roadmap, and advocate technical expertise for design wins in data centers and networking markets.

Manage an assigned US territory of long-tail accounts to drive customer expansion and revenue growth. Use digital marketing and distributor channels to scale engagement, qualify opportunities, engage engineering and sourcing teams, advance deals toward design-in and wins, maintain pipeline and forecasts, and coordinate with distribution partners for demand generation and opportunity tracking.

Lead and perform custom analog and full‑custom digital layout at chip and block levels using Cadence Virtuoso; develop floorplans, power distribution, device‑matching, verify DRC/LVS/ERC, support tape‑out, mentor junior and offshore layout engineers, and standardize layout methodologies and processes.

Lead block-level chip planning and perform custom analog and full-custom digital layout for CMOS/BiCMOS circuits. Develop floorplans, power distribution, shielding, and device-matching layouts; execute schematic-driven layouts, verify DRC/LVS/ERC, support chip integration and tape-out, mentor junior/offshore engineers, and improve layout processes and workflows.

Develop, validate, and release production test programs and hardware for ATE and oven-based trimming systems. Support NPI, tester/hardware bring-up, debugging, correlation, validation, and release documentation. Collaborate cross-functionally to improve test coverage, efficiency, manufacturability, and data-driven yield improvements.

Develop, validate, and release production test programs and hardware for ATE and oven-based trimming systems. Lead hardware bring-up, tester correlation, validation, and qualification. Collaborate with product, design, manufacturing, and quality teams to support NPI, optimize test coverage and time, maintain documentation, and drive data-driven yield improvements.

The MEMS Development Engineer will design and characterize MEMS devices, enhance automated infrastructure, run experiments, and collaborate with cross-functional teams.

Develop micro-architecture specifications, implement RTL design, verify RTL behavior, run synthesis tools, and collaborate across teams on digital design projects.

Lead Oracle Fusion Cloud applications projects, bridging technical and finance teams, providing expertise, troubleshooting issues, and managing end-user training.

Lead global supply chain strategy, optimizing supplier networks and integrating analytics to enhance operational efficiency while mitigating risks within the semiconductor sector.