Seeking a Senior Layout Designer with 10+ years of experience in high-speed low noise layout design and expert in Cadence tools.

Develop high-end ADC/DAC designs for optical communication, focusing on layout engineering in advanced processes and tape-out procedures.

Seeking an Embedded Software Engineer with 10+ years of experience to develop and maintain a Linux-based chip management application, implement testing frameworks, and optimize processes while collaborating with international teams.

The role involves backend design, focusing on RTL2GDSII flow, logic synthesis, DFT, floorplanning, and low power design techniques.

Design and develop innovative communication systems as a VLSI Design Engineer, focusing on architectural challenges and detailed implementation.

The Senior Verification Engineer will lead RTL design verification activities, build verification environments using SystemVerilog and UVM, and work with design engineers for debugging and coverage collection.

Seeking a Senior VLSI Back-End Engineer to work on high frequency and low-power budget designs, focusing on the RTL2GDSII flow and vendor collaboration.

Seeking a Senior Back End Engineer with over 10 years of experience in backend design, responsible for complex RTL2GDSII flows, low power design, and vendor collaboration.

The role involves verifying digital design blocks, building verification environments using SystemVerilog and UVM, and collaborating with design engineers to ensure full functionality coverage.

The VLSI RTL Designer will create innovative communication systems, tackle architectural challenges, and detail implementation with strong Verilog/System-Verilog skills.

The DFT Engineer will define and implement advanced DFT methodologies for complex digital and mixed-signal chips, focusing on silicon test strategies and DFT features.

The Analog Layout Designer will develop high-end ADC/DACs for optical communication, requiring expertise in layout tools and design technology.

The Senior Verification Engineer will verify digital design blocks, build verification environments using SystemVerilog and UVM, and work closely with design engineers.

The Engineering Site Manager will lead the Austin site, manage teams across various engineering disciplines, and ensure alignment with global operations. Responsibilities include establishing site goals, overseeing daily operations, and contributing to strategic planning.

Join a startup as a Backend Engineer to work on RTL2GDSII flow and low-power design, collaborating with external vendors on complex projects.

Design and verify advanced analog mixed signal circuits, focusing on ADC/DAC for optical communication. Requires extensive experience in relevant analog circuits and integrated circuit development.