Jobs at Retym

Hands-on system integration role focused on optical-module testing, customer-platform integration, silicon and board bring-up, validation, and root-cause debugging. Responsibilities include developing Python/MATLAB automation, operating laboratory equipment, analyzing signal integrity and system performance, debugging hardware and firmware, reviewing schematics, documenting findings, and supporting customer evaluations and demonstrations.

The Analog Design Engineer will develop high-end ADC/DAC systems for optical communication, focusing on design and verification of complex analog circuits in advanced processes.

Lead and manage a team of verification engineers, define verification strategies, oversee development of environments, and foster technical excellence.

Design and implement VLSI communication systems, collaborating on micro-architecture, RTL coding, verification and debugging while optimizing performance and documenting designs.

Develop and maintain a Linux-based chip management application, implement testing frameworks, optimize processes, and collaborate with international teams in embedded software engineering.

We are looking for entry level layout engineers to develop high-end ADC/DAC for optical communication in advanced processes.

Develop high-end ADC/DAC in advanced processes for optical communication, requiring expertise in layout design and Cadence tools. Teamwork and understanding of schematic flow are essential.

The System Director Manager leads the development and implementation of optical DSP systems, guiding a team of engineers and managing projects to ensure quality delivery, while driving innovation and collaboration across departments.

The Mixed Signal Verification Engineer will develop verification strategies, write testbenches, run simulations, and ensure the correctness of mixed-signal designs using UVM and SystemVerilog.

Develop verification strategies for mixed-signal designs, create behavioral models, and perform validations using UVM methodologies and SystemVerilog.

Develop verification strategies for mixed-signal designs, create behavioral models, write and debug testbenches, and run simulations to ensure model accuracy.

The Engineering Site Manager will establish and lead the Austin engineering site, overseeing operations, mentoring teams, and driving technical execution in collaboration with global teams.

Seeking a Senior Analog Design Engineer to lead the development of complex analog systems for optical communication with over 10 years of experience in analog design.

Lead RTL design verification efforts, manage test bench architecture, and mentor team members. Requires extensive experience in VLSI verification and digital design blocks.

The DFT Tech Lead will define and implement advanced DFT methodologies for complex chips, focusing on DFT strategy, architecture, and debug specifications.

Develop high-end ADC/DAC for optical communication; must have 5+ years in analog circuits, design, development, and verification.

Join the silicon design team as a Junior ASIC Back-End Engineer, focusing on physical design and timing closure, while learning from experienced engineers.

The role involves full backend implementation from RTL to GDSII, ensuring design success with a focus on low power and timing closure. Collaboration with design teams and CAD scripting are key responsibilities.

The role involves developing verification strategies for mixed-signal designs, creating behavioral models, and debugging testbenches using UVM and SystemVerilog for high-speed communication technology.

The Senior Verification Engineer will oversee RTL design verification, build test environments, mentor team members, and collaborate on design specifications.