Join a start-up as an entry-level layout engineer focused on developing high-end ADC/DAC for optical communication, requiring a year of related experience.

We are seeking a Junior ASIC Back-End Engineer to assist in physical design and timing closure for silicon design projects. Candidates should have a foundational understanding of VLSI concepts and a willingness to learn advanced design flows and tools on modern technology nodes.

Lead and manage a team in RTL design verification, defining strategies, overseeing development, debugging issues, and reporting progress.

The Algorithm Engineer will design, simulate, and optimize DSP algorithms for coherent optical transceivers while collaborating with various engineering teams.

The Senior Layout Designer will develop high-end ADC/DAC for optical communication, requiring expertise in Cadence tools and TSMC technologies.

Seeking an Embedded Software Engineer with 10+ years of experience to develop and maintain a Linux-based chip management application, implement testing frameworks, and optimize processes while collaborating with international teams.

Lead and manage the DFT team, overseeing the DFT lifecycle for ASICs and SoCs, while ensuring DFT integration, test quality, and team growth.

Design and validate high-speed multi-layer PCBs, perform signal and power integrity simulations, and collaborate with cross-functional teams.

Lead the design and development of complex ASIC architectures, focusing on RTL design, optimization, and integration with cross-functional teams while mentoring junior engineers.

Seeking a Senior Layout Designer with 10+ years of experience in high-speed low noise layout design and expert in Cadence tools.

The Senior Verification Engineer will verify digital design blocks, build verification environments using SystemVerilog and UVM, and work closely with design engineers.

Design and verify advanced analog mixed signal circuits, focusing on ADC/DAC for optical communication. Requires extensive experience in relevant analog circuits and integrated circuit development.

The Senior Embedded SW Engineer will lead firmware development, collaborate with engineers, ensure project deadlines are met, and provide technical guidance.

The Mixed Signal Verification Engineer will develop strategies for mixed-signal designs, write testbenches, perform simulations, and validate behavioral models using advanced verification tools.

The Engineering Site Manager will lead the Austin site, manage teams across various engineering disciplines, and ensure alignment with global operations. Responsibilities include establishing site goals, overseeing daily operations, and contributing to strategic planning.

The role involves verifying mixed-signal designs through behavioral modeling and dynamic verification, requiring collaboration and strong communication skills.

The role involves verifying digital design blocks, building verification environments using SystemVerilog and UVM, and collaborating with design engineers to ensure full functionality coverage.

The DFT Engineer will define and implement advanced DFT methodologies for complex digital and mixed-signal chips, focusing on silicon test strategies and DFT features.

The role involves backend design, focusing on RTL2GDSII flow, logic synthesis, DFT, floorplanning, and low power design techniques.

The Analog Layout Designer will develop high-end ADC/DACs for optical communication, requiring expertise in layout tools and design technology.