Senior MXS Verification engineer

Reposted 2 Days Ago
Hiring Remotely in Austin, TX, USA
Remote or Hybrid
Senior level
Semiconductor • Manufacturing
The Role
The role involves developing verification strategies for mixed-signal designs, creating behavioral models, and debugging testbenches using UVM and SystemVerilog for high-speed communication technology.
Summary Generated by Built In
Description

For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Sr Mixed signal verification engineer.

Requirements

Key Responsibilities:

  • Develop verification strategies for digital and analog (mixed-signal) designs, utilizing UVM methodologies based on specifications.
  • Create behavioural models for analog blocks in accordance with guidelines provided by analog designers.
  • Write, execute, and debug testbenches using UVM methodology and SystemVerilog code for mixed-signal blocks.
  • Run and debug behavioural model (BM) validation using AMS tools to ensure the correctness of the behavioural models.
  • Perform and troubleshoot unit-level, cluster-level and top-level simulations of mixed-signal designs.

Minimum Qualifications

  • 10+ years of experience
  • Experience in Behavioural Modelling (BM) of Analog design for digital verification
  • Knowledge in Mixed Signals dynamic Verification using chip digital design tools [no AMS]
  • Experience in Verilog/SystemVerilog coding
  • Experience in Virtuoso Schematics tools
  • Basic knowledge in Analog design

Preferred Qualifications

  • Experience in UVM
  • Experience in both Synopsys and Cadence tools is an advantage

Additional Skills

  • Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases.
  • Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.
  • Communication: Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multi-functional teams.

Skills Required

  • 10+ years of experience
  • Experience in Behavioral Modelling of Analog design
  • Knowledge in Mixed Signals dynamic Verification
  • Experience in Verilog/SystemVerilog coding
  • Experience in Virtuoso Schematics tools

Retym Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Retym and has not been reviewed or approved by Retym.

  • Fair & Transparent Compensation Pay is positioned as a relative bright spot compared with broader company sentiment, with compensation rated more favorably than overall sentiment in the available snapshot.
  • Strong & Reliable Incentives Good incentives are described alongside work-life balance in one public summary, suggesting rewards may be a meaningful part of the package for some employees.
  • Wellbeing & Lifestyle Benefits Meal support is implied by mention of Grubhub among “pros,” indicating at least some lifestyle/perk coverage may exist for certain teams or locations.

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The Company
Tel Aviv
7 Employees
Year Founded: 2021

What We Do

We are a semiconductor startup that has brought together a world-class team of ASIC designers, optical communications experts and seasoned investors that excel at creating disruptive technologies. Together, we are building a novel semiconductor technology that will transform the datacenter and telecommunications industries.

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