Teams at Retym

Develop, maintain, and optimize high-performance SystemC/TLM models for ASIC and optical systems. Translate DSP algorithms from MATLAB to SystemC, create executable reference models, integrate models into mixed-language verification flows, collaborate with architecture/RTL/verification teams, and support system-level debugging and performance analysis.

The Senior Embedded SW Engineer will lead DSP firmware development, provide technical guidance, and collaborate with cross-functional teams to drive project success.

The Analog Design Engineer will develop high-end ADC/DAC systems for optical communication, focusing on design and verification of complex analog circuits in advanced processes.