Jobs at MosChip

Design and validate high-speed digital, analog, and power hardware for server-class and embedded platforms. Responsibilities include architecture, schematic capture, circuit and signal integrity analysis, PCB coordination, board bring-up, debugging, system validation, documentation, and production readiness. The engineer collaborates with firmware, software, BIOS, device driver, mechanical, EMC, SI, and QA teams while using Cadence Allegro, Altium Designer, Python, and Perl.

Leads ASIC physical design for advanced-node silicon products, including floorplanning, partitioning, placement, clock-tree synthesis, routing, timing and signal-integrity closure, ECOs, power planning, and physical verification. Mentors engineers, leads block closure, interfaces with front-end ASIC teams, and applies low-power techniques such as voltage islands, power gating, and substrate biasing. Requires expertise with Cadence or Synopsys tools, PrimeTime, Perl, Tcl, and 7nm-or-smaller designs.

Develop ASIC and chip-level verification environments using SystemVerilog, UVM, C/C++, and scripting. Create verification plans, tests, assertions, coverage models, regression automation, and debug workflows to achieve tapeout readiness. Collaborate with architects, designers, and system engineers while validating hardware, software, and industry-standard protocols. Experience with simulators, waveform/debug tools, formal verification, and processor platforms is valuable.

Develop ASIC and chip-level verification environments using SystemVerilog, UVM, C/C++, and scripting. Create verification plans, tests, assertions, coverage models, regression automation, and debug workflows to achieve tapeout readiness. Collaborate with architects, designers, and system engineers while debugging software and hardware issues. Experience with simulators, formal verification, industry protocols, and processor platforms is advantageous.

Develops and manages design-for-test solutions for complex multi-million-gate SoCs, including Scan and MBIST for mixed-signal IP. Oversees test tool development, semiconductor design and manufacturing activities, silicon bring-up, debugging, and cross-functional hardware, firmware, and software integration. Leads global teams, develops managers and individual contributors, manages schedules and risks, and delivers quality semiconductor products within cost and time-to-market objectives.

Leads DFT and test development for complex multi-million-gate SOCs with mixed-signal IP. Defines scan, MBIST, and ATE solutions across the SOC design and manufacturing lifecycle, including RTL, synthesis, implementation, timing, verification, characterization, and silicon bring-up. Manages technical teams, tool development, software-related tasks, global collaboration, project execution, risk, quality, cost, and schedules.

Manages contract workforce profitability by evaluating candidates, reviewing costs and margins, tracking utilization, validating vendor invoices and timesheets, supporting rate negotiations, and preparing monthly MIS reports. Coordinates with HR, Sales, and Finance to control contractor deployment, billing, budgets, and commercial terms. Recommends contractor continuation, redeployment, replacement, or exit based on financial performance.

Generate and qualify outbound leads across India through email sequences, LinkedIn outreach, and cold calling. Use sales intelligence and CRM tools to nurture prospects, understand customer pain points, and communicate qualified opportunities to field sales teams. The role requires explaining embedded and digital engineering solutions in business terms, collaborating with sales colleagues, and working in a target-driven environment.

Lead ASIC design engineer responsible for RTL and logic design, complex SoC design and integration, multi-clock and asynchronous interface development, and ASIC verification activities. The role uses Verilog/SystemVerilog, lint and CDC tools, synthesis, timing analysis, ECO fixes, formal verification, and AMBA protocols including AXI, AHB, and APB. Strong communication, collaboration, creativity, and initiative are required.

Design complex, high-density, high-speed analog, digital, RF, and mixed-signal PCBs for server-class and HDI platforms. Create libraries and footprints, establish electrical constraints, route high-speed interfaces, design power supplies, and address power integrity, thermal, and reliability requirements. Generate and validate manufacturing data, manage PCB-to-mechanical conversions, and support release processes. Collaborate with signal and power integrity, mechanical, manufacturing, DFM/DFA, and CAD teams using major PCB design tools.

Implement and verify DFT solutions for complex SoC and ASIC designs across scan, compression, ATPG, JTAG, boundary scan, MBIST, memory repair, hierarchical DFT, simulation, timing constraint debugging, silicon bring-up, and tape-out activities. The role requires Siemens Tessent expertise, scripting in TCL or Perl, strong debugging skills, and successful advanced-node design experience.

Design and integrate complex SoCs using RTL, Verilog, and SystemVerilog. Develop multi-clock and asynchronous interfaces, apply ASIC development tools including lint and CDC, and support synthesis, timing analysis, ECO fixes, and formal verification. Implement and work with AMBA protocols including AXI, AHB, and APB, while contributing to clock and reset architecture. Collaborate effectively and communicate clearly across engineering teams.

Perform static timing analysis and timing closure/signoff across pre-CTS to post-CTS stages. Interpret timing constraints, analyze design details and reports, and apply advanced STA concepts for sub-14nm technologies. The role requires DCD knowledge and preferably expert-level proficiency with PrimeTime and Tempus. Candidates should hold a B.Tech or M.Tech in ECE and have 5–12 years of experience.

Drive revenue growth for MosChip’s product engineering services across the Eastern and central U.S. Build new customer pipelines, identify opportunities, present value propositions, close contracts, meet sales quotas, and develop relationships with director- and VP-level executives. The role targets industrial sectors including automotive, robotics, oil and gas, appliances, climate technology, eMobility, and MedTech/BioTech, requiring engineering services sales experience and technical pre-sales capabilities.

Designs and debugs analog circuits, including SerDes components, while meeting PPA and performance goals. Collaborates with layout teams to resolve design issues, generates sign-off design views, completes QA checks, prepares design reviews, and closes action items. Requires strong AMS design-flow fundamentals, familiarity with SPICE simulation tools, schedule ownership, quality delivery, and client communication. The role requires 3–10 years of experience and a bachelor’s degree in engineering, with a master’s preferred.

Design and integrate RTL for complex ASIC and SoC projects using Verilog/SystemVerilog. Develop multi-clock and asynchronous interfaces, apply lint and CDC analysis, support synthesis and timing analysis, execute ECO fixes, and perform formal verification. The role requires knowledge of AMBA AXI, AHB, and APB protocols, as well as SoC clocking and reset architectures. Strong communication, collaboration, curiosity, and a proactive approach are expected.

Leads ASIC logic design and RTL development for complex SoCs. Responsibilities include SoC design and integration, multi-clock and asynchronous interface design, Verilog/SystemVerilog coding, lint and CDC analysis, synthesis and timing evaluation, ECO fixes, formal verification, and implementation of AMBA protocols including AXI, AHB, and APB. Requires strong communication, collaboration, creativity, and motivation to learn.

Analyze timing constraints, design details, and timing reports from pre-CTS through post-CTS stages. Perform timing closure and signoff for physical design domains, applying in-depth STA concepts for sub-14nm technologies and DCD knowledge. Expertise with PrimeTime and Tempus is preferred.

Designs and integrates complex SoCs using RTL, Verilog, and SystemVerilog. Responsibilities include multi-clock and asynchronous interface design, ASIC development tooling such as Lint and CDC, timing and synthesis analysis, ECO fixes, formal verification, and AMBA protocol implementation. The role also requires understanding SoC clocking and reset architecture, strong communication, collaboration, creativity, and proactive learning.

Leads DFT and test development for complex multi-million-gate SOCs with mixed-signal IP. Defines scan, MBIST, ATE, and manufacturing test solutions; provides technical direction across SOC design, verification, characterization, silicon bring-up, and tool development. Manages engineers and managers, oversees software-related tool tasks, coordinates global teams, influences stakeholders, and delivers against quality, cost, schedule, and risk objectives.