The Role
Implement and verify DFT solutions for complex SoC and ASIC designs across scan, compression, ATPG, JTAG, boundary scan, MBIST, memory repair, hierarchical DFT, simulation, timing constraint debugging, silicon bring-up, and tape-out activities. The role requires Siemens Tessent expertise, scripting in TCL or Perl, strong debugging skills, and successful advanced-node design experience.
Summary Generated by Built In
Senior DFT Engineer | California (Onsite)
We are looking for a Senior DFT Engineer to support the implementation and verification of DFT solutions for complex SoC/ASIC designs. The ideal candidate will have hands-on experience across the full DFT flow, from scan implementation through ATPG, MBIST, and silicon bring-up activities.
Key Requirements:
- 3 to 8 years of experience in DFT for SoC/ASIC designs
- Strong experience with Scan, Compression, ATPG, JTAG, and Boundary Scan
- Hands-on experience with MBIST implementation, verification, and Memory Repair (BIRA/BISR)
- Experience with hierarchical SoC DFT implementation and verification
- Familiarity with DFT simulations, SDF timing simulations, and debugging timing constraints
- Experience with industry-standard DFT tools such as Siemens Tessent, Synopsys, or Cadence tool suites
- Scripting skills in TCL and/or Perl
- Experience with successful SoC/ASIC tape outs, preferably at advanced technology nodes (5nm or below)
- Strong debugging, problem-solving, communication, and teamwork skills
- Experience with Tessent EDA tools is a must
Location: Bay Area, CA
Work Authorization: Green Card & US citizens
Employment Type: 1099 contract.
Skills Required
- 3 to 8 years of DFT experience for SoC or ASIC designs
- Strong experience with Scan, Compression, ATPG, JTAG, and Boundary Scan
- Hands-on experience with MBIST implementation and verification
- Experience with Memory Repair, including BIRA and BISR
- Experience with hierarchical SoC DFT implementation and verification
- Familiarity with DFT simulations, SDF timing simulations, and debugging timing constraints
- Experience with Siemens Tessent, Synopsys, or Cadence DFT tool suites
- Experience with Tessent EDA tools
- Scripting skills in TCL and/or Perl
- Experience with successful SoC or ASIC tape-outs
- Experience with advanced technology nodes of 5nm or below
- Strong debugging, problem-solving, communication, and teamwork skills
- Green Card or United States citizenship
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The Company
What We Do
Established in 1999, MosChip is the first fabless semiconductor company publicly traded in India with approximately 20 years of experience. MosChip is a semiconductor and system design company with a focus on turnkey ASICs, mixed signal IP and semiconductor, product engineering and IoT solutions catering to aerospace and defense, consumer electronics, automotive, medical and networking and telecommunications. Over the past two decades, MosChip has developed and shipped millions of ASIC connectivity ICs. MosChip’ s IoT solutions like smart lighting, smart metering and asset tracking are successfully deployed in volume.
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