Jobs at Micron Technology

The Yield Analysis Engineer will drive yield improvement activities, develop innovative NAND technologies, perform statistical analysis, and collaborate with cross-functional teams.

The Senior Engineer focuses on CVD/Diffusion process development for NAND technology, executing experiments, tool troubleshooting, and supporting manufacturing process transfer.

Develop and test SSD firmware subsystems to meet performance, endurance, capacity, functionality, and reliability requirements. Create firmware unit and functional tests, debug embedded C code, collaborate cross-functionally, report status to management, and help develop team technical capability and communication.

Lead Micron Japan’s university recruiting strategy across engineering, manufacturing, technology, and corporate functions. Build sustainable pipelines for graduates, interns, vocational talent, and emerging technical talent; manage university and industry partnerships; govern recruiting and internship programs; advise executives on workforce planning; use analytics, market intelligence, and AI-enabled practices to improve hiring outcomes; and mentor regional recruiting teams.

Monitor, maintain, troubleshoot, repair, and improve semiconductor cleanroom manufacturing equipment. Perform preventative and corrective maintenance, resolve mechanical, electrical, vacuum, software, and process issues, document maintenance activities, qualify equipment after repairs, and collaborate with production teams, engineers, sustaining groups, and vendors. Support installations, evaluations, continuous improvement projects, and technician mentoring while maintaining safety, quality, uptime, and operational efficiency.

Lead pathfinding and process development for advanced patterning (193nm immersion, EUV, High NA EUV). Develop and optimize EUV lithography modules, define mask inspection strategies, collaborate with manufacturing for process transfer and readiness, and support High NA EUV development with occasional travel.

Own and develop inspection equipment strategies and recipes to detect defects, close defect gaps, and improve automation. Partner with module owners and vendors, lead projects to improve inspection efficiency and sampling, coordinate vendor applications work, and track tool maintenance and SPC with sustaining teams.

The Track Engineer will optimize processes on Track equipment, improve productivity, and collaborate with cross-functional teams to enhance technology deployment.

Lead equipment engineering for assembly manufacturing to improve safety, quality, reliability, productivity and cost. Drive equipment strategy, lifecycle management, automation, Lean/Six Sigma improvements, and AI-enabled predictive maintenance and analytics. Build team capability, deploy Industry 4.0 solutions, and partner across functions to meet OEE, downtime, and productivity targets.

Lead electrical characterization and testing of NAND, DRAM, CMOS devices and interconnects; define and manage param business processes for global high-volume fabs; develop and deploy device characterization programs; transfer test methodologies to HVM during NPI; align test equipment hardware, param software and test algorithms; collaborate with TD, process, quality, and planning teams.

Establishes and improves semiconductor process conditions, capabilities, parameters, and management projects. Evaluates new equipment and materials, analyzes abnormalities, reduces production costs, and supports process optimization through data-driven and AI-enabled tools. Requires an engineering degree, semiconductor process or manufacturing knowledge, familiarity with equipment and process flow, statistical analysis skills, and problem-solving ability. Two or more years of experience is preferred, though fresh graduates may be considered for entry-level roles.

Leads Micron’s TPG AI transformation portfolio by defining priorities, roadmaps, governance, risks, dependencies, executive decision points, and value realization frameworks. Aligns AI investments with business outcomes, engineering transformation, and long-range planning. Partners with Finance and Business Operations on resources and capacity, builds executive reporting, and leads a program management function incorporating responsible AI, security, IP protection, governance, and organizational change.

Lead design, governance, execution, and continuous improvement of Micron's global IT Disaster Recovery program. Manage enterprise recovery planning, resilience assessments, testing exercises, recovery validation, and executive reporting. Partner with infrastructure, applications, cybersecurity, BCM, cloud, manufacturing, and leadership to align recovery strategies with RTO/RPO, compliance, and cyber resilience objectives. Drive AI-enabled automation and analytics to improve recovery effectiveness.

Lead High NA EUV initiatives at NYCreates, manage engineers and technicians, coordinate tooling and logistics, define patterning pathfinding projects, benchmark performance, develop roadmaps, and collaborate across global Micron TD sites to enable next-generation photolithography and AI-enabled solutions.

Act as Micron's technical advisor for datacenter customers to drive DRAM/HBM/SSD design wins, resolve system configuration and performance issues, guide memory architecture and optimization, support validation/lab testing and deployments, and collaborate across sales, product, and engineering teams.

Design and validate on-chip controllers and mixed-signal circuitry for NAND Flash chips. Responsibilities include architecture development, product definition, system integration, RTL implementation, synthesis, automated place and route, timing closure, firmware development, and full-chip and block-level validation. The engineer collaborates with domestic and international design teams across multiple projects.

Participate in a five-month project optimizing NAND component test flows through manufacturing data analytics, automation, statistical analysis, machine learning, and enterprise AI. Retrieve, prepare, analyze, and visualize manufacturing data; develop scripts, models, reports, and automation tools; identify product recovery and test-flow improvement opportunities; validate AI-generated outputs; and present documented findings and recommendations. Collaborate with engineers while strengthening technical documentation, communication, and problem-solving skills.

Lead analog/mixed-signal design automation for NAND circuits, implement core and array designs, run block and full-chip simulations, develop AI/LLM-assisted design flows, integrate automation with project teams, and collaborate cross-functionally to improve manufacturability, reliability, and time-to-market.

Develops and optimizes test programs for SSD and UFS controller products, improves test coverage, reduces testing time and manufacturing costs, and automates test engineering processes with software scripts. Collaborates with product, equipment, and design engineering teams to improve yield, equipment efficiency, and design-for-test capabilities. Monitors engineering metrics and supports characterization and yield reporting through data analysis tools.

Supports heterogeneous integration wafer-level engineering activities, including material planning, procurement, inventory logistics, DOE tracking, sample delivery, budget management, audits, reporting, and business-process development. The role requires knowledge of HBM wafer probe and semiconductor fabrication/test processes, MES/MAM lot management, ESD controls, safety, compliance, and continuous improvement. The engineer also uses Claude Code and AI applications to improve productivity and quality, resolves complex issues, coordinates cross-functional teams, and may mentor junior staff.