Jobs at MatX

Lead supplier diligence, market mapping, financial modeling, and deal structuring to secure semiconductor and hardware supply. Support end-to-end partner selection, negotiation, and execution while coordinating with engineering, operations, finance, and legal. Produce concise deal memos, market maps, supplier assessments, and build internal processes for supply-chain deals.

Support business development and company operations by managing scheduling, triaging communications, preparing research, tracking action items, coordinating travel and visitor logistics, and owning special projects to ensure partners, vendors, and internal teams follow through.

Lead and grow a kernel engineering team while designing and implementing high-performance compute kernels for specialized AI hardware, collaborating with ML research and hardware teams to optimize performance and integration.

Design, implement, and optimize Linux kernel drivers and low-level userspace libraries for PCIe AI accelerators. Prototype and validate features on pre-silicon platforms, perform first-silicon bring-up, debug hardware/software interactions, profile host I/O paths, deliver tests, and expose telemetry for management and BMC integration while influencing future chip architecture.

The AI Accelerator Silicon Architect will define compute architecture, analyze performance, and collaborate with teams on silicon architecture for AI workloads.

As a Formal Verification Engineer, you will ensure correctness in hardware and software by applying model checking and developing machine-checked proofs, collaborating with various teams for verification processes.

The role involves silicon micro-architecture and design, managing the complete design process from micro-architecture to sign-off, including collaboration with verification teams and achieving high-performance metrics.

As a Silicon DFT Engineer, you will design test solutions, integrate DFT functions, collaborate with various teams, and improve test quality for AGI silicon.

Lead and drive design-phase execution for rack-scale AI platforms. Maintain master schedules, track critical-path items and risks, coordinate cross-functional design and readiness reviews, engage CM/JDM partners, ensure validation readiness, and provide executive updates on milestones, risks, and resource gaps.

Design, define, and validate rack-scale power architecture for a rack-scale AI data center product. Develop power specs and estimation models, implement and validate voltage regulator designs, perform lab bring-up and workload testing, ensure compliance with safety and thermal standards, and provide technical leadership during board and system integration.

Design and optimize hardware interfaces, collaborate with ML and hardware teams, and ensure software and hardware integration.

Develop and sign-off performant silicon from RTL to GDSII across blocks, subsystems, and full-chip. Lead partitioning, floorplanning, synthesis, P&R, clocking, verification, timing/power sign-off, and collaborate with Design, Verification, and DFT teams to meet tapeout milestones.

Lead integrated NPI lifecycle for rack- and board-level AI systems, coordinating CM/JDM partners, PLM/BOM/ECO control, factory test deployment, quality and yield metrics, and high-volume ramp readiness while reporting risks and readiness to executives.

Design and implement compilers for proprietary hardware architecture, focusing on midend and backend development, while providing hardware insights.

The Executive Operations Coordinator supports the CEO and Chief of Staff by managing the CEO's calendar, communications, meeting logistics, and operational projects, ensuring smooth workflow and productivity for the leadership team.

The Architect will oversee hardware architecture, collaborate with teams, and enhance silicon design performance for AI models.

Develop and execute Rust tests to verify silicon designs and software, ensuring they conform to specifications by identifying discrepancies before production.

Lead the design of next-generation AI-focused silicon by translating product requirements into SoC architectures and collaborating with teams on power and performance trade-offs.

Develop and maintain performance models of hardware, while collaborating with architecture and runtime teams. Optimize performance and contribute to architectural reviews.

As a SOC Integration Engineer, you will develop and integrate SOC RTL designs, collaborate with cross-functional teams, and ensure high-quality silicon integration.