Jobs at Delos Data

Design and implement production-ready RTL for complex digital subsystems, translating architectural specifications into scalable microarchitectures. Collaborate with architecture, verification, and physical design teams on correctness, synthesis, timing, power, and area closure. Perform linting, CDC analysis, simulation, debug, integration, and design reviews. Contribute to reusable RTL, design methodologies, tooling, and AI-assisted workflows.

Develop and maintain RTL verification environments for ASIC and FPGA designs using UVM and SystemVerilog. Create coverage-driven plans, directed and constrained-random tests, assertions, and reusable verification components. Analyze simulations, debug design issues, track functional and code coverage, automate regressions with Python, and drive verification through closure. Collaborate with RTL engineers on reviews, testability, and reliable silicon delivery while verifying protocols including AXI, APB, PCIe, Ethernet, SPI, and I²C.

Build and maintain automated testing frameworks for distributed AI training and inference workloads. Develop end-to-end integration and stress-testing plans, validate GPU and hardware-software interactions, and troubleshoot failures in large-scale distributed systems. Partner with system engineers using telemetry and profiling tools to identify bottlenecks. The role requires Python, test automation, containerization, CI/CD, and familiarity with infrastructure management tools.

Design and implement system software, communication primitives, and execution primitives for large-scale AI workloads across thousands of GPUs. Analyze and resolve distributed training and inference performance bottlenecks, investigate software-hardware interactions, and benchmark multi-node clusters. Collaborate across the technology stack to shape foundational AI infrastructure. Required skills include C++, Python, systems programming, and Linux; GPU programming and distributed AI framework experience are preferred.

Own a strategic customer's production AI infrastructure deployment, troubleshooting GPU/XPU clusters, high-speed networks, schedulers, and orchestration systems. Lead integrations, upgrades, performance tuning, automation, and root-cause analysis. Translate field problems into product features, write Python and Bash tooling, support customer evaluations and deployments, and collaborate with SRE, platform, and engineering teams. The role is on-site in Cambridge, UK, with travel as needed.

Architect and deliver advanced multi-die IC packages for high-performance AI accelerators. Responsibilities include package and substrate design, bump and ball mapping, high-speed signal routing, power distribution, manufacturability, thermal and mechanical optimization, subcontractor management, and collaboration with TSMC or OSAT. The role also supports package bring-up, failure analysis, debugging, qualification, and evaluation of emerging packaging technologies.

Develop and maintain UVM-based RTL verification environments for ASIC DFT logic. Create coverage-driven plans, directed tests, assertions, and automated regressions; verify MBIST, scan, ATPG, JTAG, boundary scan, and other DFT functionality. Debug simulation and design issues, validate gate-level behavior and tester patterns, support SoC-level and post-silicon bring-up, and collaborate with DFT design and manufacturing engineers to deliver reliable silicon.

Architect, design, integrate, and validate analog and mixed-signal technologies for high-speed PHYs and SoCs. Lead AMS architecture, circuit design, clocking, power, signal integrity, chip-package-PCB co-design, and silicon validation across interfaces such as UCIe, DDR, HBM, and SerDes. Drive designs from architecture through production, resolve cross-domain integration issues, guide external partners, establish design methodologies, and provide technical leadership and mentoring.

Own complex ASIC and SoC physical implementation from synthesized netlist through signoff, including floorplanning, placement, CTS, routing, timing closure, ECOs, physical verification, and power integrity. Lead cross-functional timing and implementation convergence, develop automation and methodologies, resolve advanced-node challenges, and provide technical mentorship. Partner with RTL, architecture, DFT, verification, package, and SI/PI teams while driving PPA, runtime, quality, and tapeout readiness.

Build and maintain automated testing frameworks for distributed AI training and inference workloads. Develop end-to-end integration and stress-testing plans covering distributed systems, GPU kernels, AI frameworks, and hardware-software boundaries. Collaborate with systems engineers to troubleshoot failures in large-scale clusters, using telemetry and profiling tools to identify root causes and performance bottlenecks. The role also supports containerized test environments and CI/CD workflows.

Build and maintain automated testing frameworks for distributed AI training and inference workloads. Develop end-to-end integration and stress-testing plans, validate GPU and hardware-software interactions, and troubleshoot failures in large-scale distributed clusters. Collaborate with systems engineers using telemetry and profiling tools to identify root causes and performance bottlenecks. The role requires Python automation, test framework development, containerization, and CI/CD experience, with Kubernetes, infrastructure automation, networking, and firmware testing experience preferred.

As a System Software Engineer, you will design communication primitives for AI models, optimize performance for training workloads, and benchmark performance on clusters.

Delos is a stealth-mode startup seeking to build foundational technology for AI data centers, fostering a collaborative and responsible working environment.