Teams at Delos Data

Architect and deliver advanced multi-die IC packages for high-performance AI accelerators. Responsibilities include package and substrate design, bump and ball mapping, high-speed signal routing, power distribution, manufacturability, thermal and mechanical optimization, subcontractor management, and collaboration with TSMC or OSAT. The role also supports package bring-up, failure analysis, debugging, qualification, and evaluation of emerging packaging technologies.

Develop and maintain UVM-based RTL verification environments for ASIC DFT logic. Create coverage-driven plans, directed tests, assertions, and automated regressions; verify MBIST, scan, ATPG, JTAG, boundary scan, and other DFT functionality. Debug simulation and design issues, validate gate-level behavior and tester patterns, support SoC-level and post-silicon bring-up, and collaborate with DFT design and manufacturing engineers to deliver reliable silicon.

Architect, design, integrate, and validate analog and mixed-signal technologies for high-speed PHYs and SoCs. Lead AMS architecture, circuit design, clocking, power, signal integrity, chip-package-PCB co-design, and silicon validation across interfaces such as UCIe, DDR, HBM, and SerDes. Drive designs from architecture through production, resolve cross-domain integration issues, guide external partners, establish design methodologies, and provide technical leadership and mentoring.