Jobs at Cadence Design Systems

Leads cross-functional teams delivering semiconductor services projects and technology initiatives from scoping through completion. Responsibilities include creating statements of work and cost plans, managing schedules, budgets, risks, resources, deliverables, customer communications, and commercial negotiations. The role partners with account, technical, finance, legal, sales, field, and services teams while driving customer satisfaction and process improvements. Occasional domestic and international travel is required.

Leads Cadence’s global physical security operations, including regional security directors, GSOC functions, Americas operations, incident response, risk assessments, access control, CCTV, vendors, budgets, and modernization initiatives. Advises executives, coordinates crisis response, establishes global standards and metrics, and integrates security operations across regions, sites, laboratories, and high-security R&D environments.

Responsible for selling Simufact simulation software to new and existing customers, providing consulting and technical support, creating marketing and technical documentation, coordinating with development teams, and collaborating across software teams to deliver customer solutions.

Develop and enhance software functionality, custom client projects, and algorithmic solutions within Cadence’s engineering software suite. Translate business requirements into effective technical solutions, optimize existing systems, and collaborate with global engineers and product managers. The role focuses on Python-based agentic AI and infrastructure, including LLMs, RAG pipelines, model serving, APIs, embeddings, vector databases, and production AI integrations.

Lead customer and foundry enablement for in-design physical verification solutions covering DRC, fill, and LVS. Deploy, debug, and optimize Innovus and Pegasus/PVS flows for advanced-node designs, validate rule decks, resolve customer issues, collaborate with R&D and field teams, and develop automation that improves verification coverage and turnaround time.

Leads semiconductor design verification strategy and execution using UVM/SystemVerilog, constrained-random testing, formal verification, and gate-level simulation. Designs reusable testbenches, develops complex sequences, analyzes coverage, debugs design issues, and oversees verification sign-off. Mentors junior engineers, coordinates with design, architecture, and emulation teams, and manages verification schedules, risks, and priorities.

Lead design verification strategy and execution for customer ASIC projects. Architect reusable UVM/SystemVerilog testbenches, develop constrained-random tests, analyze coverage, perform formal verification and gate-level simulation, debug complex design issues, and provide verification sign-off. Mentor junior engineers, manage verification schedules and risks, and collaborate with design, architecture, emulation, and customers.

Lead verification strategy and architecture for semiconductor ASIC and SoC designs. Build reusable UVM/SystemVerilog testbenches, develop constrained-random tests, perform formal verification and gate-level simulation, analyze coverage, debug complex design issues, and approve verification sign-off. Mentor junior engineers, coordinate with design, architecture, and emulation teams, and manage verification schedules, risks, and priorities.

Leads design verification strategy and architecture for customer ASIC projects. Designs reusable UVM/SystemVerilog testbenches, develops constrained-random tests, manages coverage, performs formal verification and gate-level simulation, and debugs complex design issues. Provides technical leadership through customer interaction, sign-off approval, cross-functional collaboration, project scheduling, risk management, and mentorship of junior engineers.

Develop and support Functional ECO automation technology for VLSI design. Work with Conformal ECO to generate gate-level patches from RTL modifications, enabling efficient chip updates and on-schedule semiconductor manufacturing.

Research, develop, and test advanced algorithms for logic verification, data-path analysis, machine learning, and artificial intelligence within Cadence’s Conformal EDA tools. The role supports next-generation verification technologies used by high-technology customers and contributes to challenging IC design tool projects.

Develop, implement, and test advanced algorithms for EDA verification tools, including low-power verification, logic verification, and synthesis. Contribute to Conformal product development using C/C++, with opportunities to work on logic synthesis algorithms, power intent languages, database algorithms, and multithreading. Collaborate with a diverse engineering team to deliver trusted IC design and verification technologies.

Maintain and update AI platform tooling, dependencies, integrations, CI/CD pipelines, containerized cloud services, and internal packages. Troubleshoot issues, apply security fixes, validate updates, monitor system health, and support engineering teams using shared tools and services. The role emphasizes reliability, service-oriented support, documentation, and practical maintenance rather than new architecture design.

Develop and lead reusable UVM simulation testbenches using SystemVerilog, C/C++, and RTL. Integrate formal verification and AI-driven coverage analysis, collaborate with architecture, RTL design, and software teams, and align verification plans with ISA requirements. Verify complex processor pipelines, memory subsystems, and ISA implementations while automating verification flows with Perl, Python, or Tcl and supporting processor integrations such as RISC-V or ARM with AMBA and PCIe protocols.

Lead development of ARM-based SoC subsystems using Cadence design, verification, and emulation platforms. Build and port systems to Palladium and Protium, ensure functional correctness, analyze hardware-software performance, and recommend improvements. The role requires deep RTL development and verification experience, expertise in AMBA and CHI protocols, SoC integration knowledge, and emulation experience. Familiarity with PCIe, CXL, and automated integration and verification methodologies is beneficial.

Support secure cloud-based Linux and HPC environments for external customers using silicon design platforms. Troubleshoot compute, storage, networking, identity, scheduler, performance, and licensing issues; maintain reliability and availability; automate monitoring, provisioning, and incident response with Python, shell scripting, Perl, and agentic AI. Manage ITAR/CUI compliance, participate in root cause analysis, and create operational and customer-facing documentation.

Develop high-performance C++ engines and algorithms for Innovus physical synthesis, placement, timing-driven optimization, and semiconductor design workflows. Responsibilities include graph and spatial algorithms, numerical optimization, multithreaded and distributed computing, performance profiling, memory optimization, and scalable PPA, timing, power, and congestion improvements. The role also involves translating research into production software and integrating AI-assisted optimization techniques.

Develop and support Cadence Innovus physical implementation and routing software. Responsibilities include enhancing data models, place-and-route flows, databases, performance, APIs, and class definitions; troubleshooting and debugging software; and supporting P&R design workflows. The role requires strong software engineering expertise, IC design data-model knowledge, database architecture experience, and efficient data-access algorithm skills.

Designs analog integrated circuits at Cadence. The provided description contains no further responsibilities, qualifications, or project details beyond the role title and compensation information.

Supports Windows and Linux compute farms across on-premises and cloud environments. Responsibilities include system administration, performance tuning, upgrades, workload migrations, acceptance testing, storage and networking support, troubleshooting R&D user issues, automation, and resource optimization. The role also requires collaboration with global IT and R&D teams, knowledge sharing, and applying virtualization, cloud, scripting, and DevOps capabilities.