The role involves managing the product lifecycle, coordinating with R&D and marketing for new product development, and enhancing product data automation.

Lead the design and implementation of DFT techniques, including SCAN, ATPG, and JTAG. Collaborate with cross-functional teams on chip tape out and post-silicon bring up, ensuring successful project execution.

The Senior Principal Design Engineer at Cadence will work on DFT and testing for chip designs, requiring extensive experience in ATPG, JTAG, and related methodologies. Responsibilities include chip tape out, test structure design, and cross-domain collaboration to ensure successful project execution.

The HR Intern supports daily HR operations, assists with employee lifecycle administration, manages HRIS data, and engages in recruitment activities. They promote Cadence's culture and assist with training programs and HR processes.

The Design Engineer I will design RTL for high-speed Ethernet IP cores and collaborate with design teams while learning digital design best practices.

The IT Director will oversee and manage IT infrastructure and services across multiple sites in Europe, ensuring high availability, performance, and compliance while leading global IT teams and driving operational efficiency.

Lead the development of test plans and verification infrastructure for complex SoCs, ensuring coverage closure through advanced testing methodologies and protocols.

Seeking a software engineer for the Pegasus Physical Verification System to design and develop verification software, focusing on DRC, LVS, and related tools.

The role involves interfacing with customers, capturing requirements, driving software integration, resolving issues, and defining product enhancements and quality improvements in system design.

The Senior Sales Operations Analyst will analyze data, improve sales processes, and manage quota distribution, compensation plans, and incentive programs while collaborating with teams across the organization.

Lead the Go-To-Market strategy for AI and LLM products, managing customer engagement and technical evaluations while bridging communication between R&D and customers.

Lead the design and development of Verification IP using C/C++, manage multiple VIP projects, and possess strong debugging skills in functional verification.

The Sr Principal Product Engineer will manage customer engagements for AI-powered EDA products, bridging technical needs and R&D while developing marketing materials and ensuring successful GTM initiatives.

The role involves designing, implementing, and supporting global data centers and WAN, managing network transformations, and troubleshooting complex issues.

The role involves driving Go-To-Market strategy and managing customer engagements for AI-driven chip design products, ensuring flawless technical evaluations and bridging customer needs with R&D.

The role involves maintaining Unix systems, automating operations, troubleshooting issues, and improving IT infrastructure performance globally within a large team.

The FP&A Staff Financial Analyst will analyze budgets, forecasts, and assist in financial decision-making for the IT organization, enhancing financial transparency and optimizing costs.

The Design Engineering Architect role involves developing PHY architecture, aligning with JEDEC standards, engaging in customer-facing technical support, and collaborating across teams to ensure successful implementation and influence future technology roadmaps.

The intern will work with the Verification Management group to build ML capabilities for classifying design and testbench code changes to detect bugs early.

The internship introduces basic skills in analog and digital IC design for high-speed communication circuits, using Cadence tools to design and implement IC circuits while participating in team meetings.