Jobs at Cadence Design Systems

Provide expert technical support and enablement for custom IC front-end solutions with a focus on analog simulation (Spectre/SPICE) and AI-enabled design/debug flows. Perform demos, training, customer evaluations, onsite debugging, and manage technical issues. Collaborate with R&D, sales, and product teams to validate AI-driven workflows and drive technology adoption.

Lead design and development of high-speed memory IP (GDDR7/DDR5/LPDDR6). Perform analog design, layout, digital integration, documentation, silicon validation, and customer-facing discussions throughout full IP lifecycle from specification to silicon characterization.

Provide expert-level technical support and enablement for custom IC front-end solutions with emphasis on analog SPICE simulation and adoption of AI-assisted analog design flows. Deliver demos, trainings, onsite debugging, customer issue tracking, and feedback to R&D and product teams to improve workflows and automation.

Customer-facing pre-sales engineer driving Palladium hardware emulation evaluations, demos, and benchmarks; enable customer adoption, optimize verification flows, provide hands-on support, and feed product insights to R&D and marketing.

Lead Foundation IP quality and product validation for standard cells, IO libraries, and memory compilers. Drive QA strategies and sign-off, perform QA reviews (DRC/LVS, timing, reliability), analyze silicon and customer data, collaborate with design/validation/customers, and mentor engineers to improve manufacturability and reliability.

Develop and optimize parasitic extraction software (Quantus) including algorithm design, high-performance C++ coding, debugging, memory and performance optimization, GUI integration, and collaboration with cross-functional teams to deliver production-quality EDA tools and support customer issues.

Support customer projects for Cadence Clarity and Sigrity by validating electromagnetic simulation tools against measurements and references, collaborate with developers to improve tools, automate workflows with basic scripting, and prepare application notes and simulation guidelines.

Work with sales and engineering to scope and run technical evaluations, benchmarks, trainings, demos and customer projects for Cadence Verification Division products. Provide technical expertise to resolve customer queries, drive product feedback, and support sales/marketing alignment.

Provide technical support in backend digital design, involving Place and Route and timing/power signoff, while guiding customers on Cadence technologies and improving methodologies.

Responsible for developing Pegasus, a parallel verification product, and contributing to case analysis, bug fixes, and feature development.

Drive product engineering for Cadence Genus synthesis solution to improve Power, Performance & Area. Verify new features, perform experiments, debug physical-aware synthesis issues, and ensure interoperability with other Cadence tools. Support field engineers and customers, document product requirements, and bridge synthesis with place-and-route flows.

Lead customer-facing backend digital implementation and signoff for RTL-to-GDSII flows, optimizing power, performance, and area. Drive technical strategy, support flagship tapeouts, develop and augment flows using scripting, and collaborate with R&D to improve tools and methodologies.

Entry-level, cohort-based rotational role providing front-line EDA application support, technical sales assistance, and design services. Work with customers and internal teams on digital/analog design, verification, simulation, physical design, timing/power/SI sign-off, embedded HW/SW co-verification, and hardware emulation. Two six-month technical rotations followed by placement in a CST business group.

Customer-facing senior technical account leader who defines and executes account technical strategies for the Cadence SVG platform. Acts as trusted advisor, communicates customer needs to internal teams (AE, R&D, business unit), drives technical campaigns globally, and owns all customer interactions for strategic accounts.

Embed with strategic semiconductor customers to deploy LLM- and agent-based AI into end-to-end EDA flows (RTL through signoff). Architect agentic workflows, integrate Cadence AI products, define KPIs for productivity and ROI, guide secure LLM access and infrastructure, run design reviews, and produce reusable playbooks to scale deployments across sites.

Lead a worldwide account team to drive adoption and growth of Cadence solutions. Build sales pipeline, consult with executive customers on design/system requirements, architect solutions using EDA software, IP, hardware and services, and advocate customer needs across Cadence to ensure long-term success and roadmap alignment.

Provide expert pre-sale and post-sale technical support to customers in back-end physical design. Work on floorplanning, place-and-route, clock tree synthesis, and STA. Collaborate with engineers and business teams, present solutions, and leverage EDA tools (Cadence) to solve complex semiconductor design problems.

Support pre-sale and post-sale activities for Cadence PCB and simulation solutions: deliver demos, trainings, technical presentations, diagnose customer issues, recommend solutions, feed product feedback to R&D, and collaborate with sales and engineering teams across Europe. Occasional travel for customer visits and internal training required.

Customer-facing technical lead performing SI and PI analysis for IC packages and PCBs using Sigrity and Clarity 3D. Tasks include PDN/IR drop optimization, time/frequency domain simulations, IBIS/IBIS-AMI testbench design, EM extraction, protocol sign-off (DDR5/LPDDR5/PCIe5), customer training, presentations, and on-site customer support across France.

Lead development and support of chip power integrity, IR, and EM analysis tools and workflows. Solve electrical circuit and numerical/graph algorithm problems, model interconnects, package and die, write automation in Python/Tcl, and collaborate with EDA and semiconductor teams to drive IR/EM sign-off solutions.