Jobs at Cadence Design Systems

The Principal Program Manager coordinates R&D Development Projects and manages customer engagement, ensuring project success through collaboration and effective execution.

The Design Engineer II role focuses on post-silicon testing and validation of Analog and Digital IP solutions, requiring leadership in lab tests and silicon characterization while collaborating with remote teams.

Develop Formal Verification IPs, including Verilog design models and System Verilog Assertions for industry standard bus protocols, while collaborating across teams.

The role involves certifying the Cadence Innovus Platform, collaborating with RD and foundry partners, and supporting customers with technical challenges.

The Lead Product Engineer will certify the Cadence Innovus Platform, collaborate with RD and foundry partners, and resolve complex technical issues for customers.

The Principal Design Engineer will work on PCIe design, focusing on high-speed interfaces and collaboration with DV teams to optimize designs and address issues.

The Software Engineer II role involves developing and supporting physical verification tools, debugging software, and optimizing algorithms while collaborating with EDA professionals.

The Lead Software Engineer will focus on pre-silicon verification, applying AI techniques, collaborating with machine learning teams, and utilizing EDA tools to enhance verification methodologies.

The role involves managing and supporting cloud infrastructure, optimizing HPC clusters, and collaborating with engineering teams for performance improvements and operational efficiency.

The Lead Software Engineer will drive pre-silicon verification using AI, collaborate with teams, and develop advanced verification methodologies.

The Principal Design Engineer manages technical issues, verifies and integrates system-on-chip components, trains customers, and leads product improvements with strong technical skills and customer engagement.

The role involves leading customer engagement in IC design and providing support in design flows, simulation, and semiconductor processes.

Develop software solutions, analyze algorithms, collaborate on architecture, code review, and document design. Requires strong C/C++ proficiency and problem-solving skills.

Focus on high-speed digital DDR PHY IP physical implementation, enhancing design flow through scripts and tools while solving project tasks and optimizing processes.

Manage HR strategies, oversee administration, enhance employee relations, improve HR processes, lead initiatives, optimize structures, and support development programs.

The Circuit Analysis Engineer will design, implement, and maintain software for transistor-level circuit simulation using AI frameworks, collaborating with engineering teams.

Join Cadence as a Software Engineer II to enhance the Virtuoso platform's routing capabilities, leveraging machine learning and advanced algorithms in a collaborative environment.

The Mixed-Signal Systems and Verification Engineer II will develop simulation-efficient behavioral models, verify complex designs, debug failures, and maintain verification infrastructure, collaborating across teams.

This role involves leading the bring-up and debugging of SerDes PHY IPs, conducting performance analysis, and collaborating with firmware teams. Candidates should possess extensive experience in silicon bring-up and PCIe protocols.

The Lead Verification Engineer will enhance pre-silicon verification through AI technologies, collaborating with software and machine learning teams to innovate and validate methodologies.