Jobs at Cadence Design Systems

Lead customer engagements to support critical analog design projects, deploy analog design automation innovations, collaborate with Product Engineering and R&D, and provide scripting and tooling support to solve complex customer problems.

Lead a team to ensure semiconductor designs meet TSMC reliability standards by managing deployment and optimization of PERC flows to detect complex electrical failures such as ESD and latch-up. Oversee validation, rule development, and flow improvements to prevent reliability issues prior to manufacturing, coordinating with design and manufacturing stakeholders.

The role focuses on driving customer engagement, developing business strategies, supporting cloud products, managing partnerships, and coordinating with stakeholders to enhance Cadence's cloud business.

Develop and maintain the Palladium logic synthesizer, add VHDL/Verilog feature support, optimize logic and performance, and collaborate across sites. Support design modeling and verification workflows.

Provide tools and hands-on support to analog circuit and custom layout teams using Cadence EDA tools. Support design capture, pre/post-layout simulation, optimization, EM/IR and thermal analysis, reliability and 2.5D/3D IC flows, and develop AI-driven tooling and improvements to increase efficiency and quality.

Design, develop, and optimize high-performance algorithms and electromagnetic field solvers. Improve performance, accuracy, and scalability of tools, participate in architecture decisions, and collaborate with cross-functional teams to deliver robust R&D software solutions.

Develop partitioning and optimization algorithms and new features for the Protium prototyping platform. Collaborate with geographically distributed teams on implementation specs, and work with technical support and customers to troubleshoot implementation and usage issues.

Develop and drive low-power verification flows for Xcelium, collaborate with R&D and AE, work with top-tier customers to deploy solutions, create product requirements, automate tool flows, and document best practices.

Design and implement high-speed, high-accuracy analog cells, blocks, and IP using advanced foundry nodes. Build layouts and methodologies, collaborate with global circuit designers and Cadence R&D (Virtuoso/PVS) to develop layout/verification tools, and meet technical and schedule requirements with high quality.

Design and develop system-level accelerated verification IP (AVIP) solutions for emulation/prototyping platforms. Build and integrate AVIP environments, create end-to-end verification flows, architect multi-protocol system validation, optimize emulation performance, develop test cases and automation, collaborate with cross-functional teams, and support customer bring-up, debug, and deployment.

Lead Product Engineer focused on Static Timing Analysis (STA) and signoff tool (Cadence Tempus) development and deployment. Responsibilities include defining specifications for tool enhancements, collaborating closely with R&D to mature features (including ECO support), and delivering capabilities per customer requirements while working as a strong team player.

Lead customer engagements to drive adoption of Cadence digital implementation, physical design, and static verification flows. Perform floorplanning, power grid design, place-and-route, CTS, timing closure, and low-power methodologies for advanced nodes (7nm and below). Influence methodology and flow development, collaborate with RTL teams, R&D, and product engineering to ensure successful tapeouts and PPA optimization.

Provide expert FEA/CAE technical support, develop CAE models and automation scripts, run benchmarks and evaluations, deliver trainings and demos, create technical documentation, and collaborate with sales, R&D, and marketing to expand Cadence product adoption.

The Sr Principal SI/PI Engineer role involves optimizing high speed IP products, package design, simulation, and customer support for SI/PI inquiries.

Develop the Virtuoso Heterogenous Integration product, ensure a high-performance design environment, and work on multi-fabric systems.

Lead technical evaluations and benchmarks for verification products, support sales with demos and trainings, ramp customer projects, provide expert technical support, and align customer feedback with product engineering and marketing for feature improvements.

The Technical Program Manager will oversee R&D projects and customer engagements, ensuring effective project execution, stakeholder communication, and team collaboration.

Provide expert field applications engineering for digital implementation and signoff, guiding customers on Cadence synthesis, place-and-route, timing and power closure. Drive technical evaluations, demos, benchmarks, and tool adoption; collaborate with R&D to influence product direction and improve flows using scripting and best practices to meet PPA and design closure goals.

The Software Architect will design, develop, and maintain software for physical verification of semiconductor devices, solving complex challenges and collaborating with a global team.

The role involves developing advanced algorithms for extraction processes and collaborating with multiple teams to ensure feature delivery.