Search the 302 jobs at Cadence Design Systems

As a Principal Design Engineer at Cadence, you will be responsible for the development and verification of hardware and software safety mechanisms, implementing test benches, and ensuring product certification for functional safety in embedded processor technology. You will work closely with various teams and contribute to documentation for safety certification.

The Software Engineer II will design, develop, troubleshoot, and debug software programs for a physical synthesis core engine while collaborating with a global R&D team and providing engineering solutions to customers.

The Principal Design Engineer at Cadence will lead the Functional Safety Design Verification Team, focusing on hardware and software safety mechanisms for Xtensa processors. Responsibilities include developing test benches, conducting fault simulations, and delivering safety documentation following ISO 26262. The role also involves close collaboration with RTL and EDA teams.

The Sr Principal Software Engineer at Cadence involves R&D support for product engineers, troubleshooting, and developing features to enhance synthesis results. The role emphasizes research and mentoring while focusing on developing scalable Modus DFT software and tools using C/C++.

The Principal Design Engineer at Cadence is responsible for developing test plans and verification infrastructure for complex IPs and SoCs. This role involves creating verification environments using UVM and developing reusable models and coverage-driven verification techniques. Strong mentorship and individual contributor experience are essential.

Develop and maintain tools for Process Design Kits (PDK) Validation, involving collaboration with teams and customers to understand requirements. Responsibilities include designing, implementing, and testing software, ensuring quality and enhancement for current software releases, while working within a global R&D organization.

The Lead Design Engineer at Cadence is responsible for leading design projects that create innovative technological solutions, contributing to impactful advancements in the tech industry.

The Principal Software Developer will lead the software architecture for chiplets, contribute to design and planning efforts, and define development processes. Responsibilities include collaborating with stakeholders, guiding the team technically, and ensuring high-quality software through structured coding guidelines and reviews.

The Lead Software Developer at Cadence will focus on embedded software development, working on device drivers and board support packages. Responsibilities include developing for USB, PCIe, Ethernet, and UCIe controllers. The role emphasizes innovation and teamwork within a diverse technological environment.

The Lead Software Engineer at Cadence is responsible for designing and developing advanced software programs while evaluating complex problems and providing scalable solutions. The role includes producing design specifications, mentoring team members, and working independently with cross-functional teams to enhance software performance.

The Principal Verification Engineer will be responsible for validating upcoming features in Palladium technologies, managing current regressions, and mentoring junior team members. The role involves technical discussions, review of specifications and test plans, and ensuring the quality of releases in the Emulation domain.

The Principal Design Engineer will work on cutting-edge technologies related to Place & Route, focusing on timing closure and low power requirements. Responsibilities include understanding physical verification and scripting languages as an advantage.

The IT Staff Systems Engineer will automate operations to manage Unix infrastructure globally, involving installation, configuration, and administration of various Linux systems. Responsibilities include working on automation projects, server builds, upgrades, and providing support for LDAP, DNS, and configuration management tools.

The Legal Counsel EMEA will support sales teams in contract negotiation and compliance, manage disputes related to intellectual property, and collaborate across departments to mitigate legal risks. They will also ensure compliance with company policies and provide training to staff.

As a Sr. Principal AE at Cadence, you will provide advanced technical support and guidance to customers in Backend Digital Design Implementation and Signoff, ensuring their design goals are met. Your role involves conducting presentations, collaborating with R&D, and enhancing workflows through programming. You'll utilize your expertise to drive adoption of Cadence technologies and improve client engagement outcomes.

The Marketing Data Analyst II at Cadence will leverage advanced data analysis skills to derive strategic insights that drive marketing decisions, develop dashboards using Tableau, and collaborate with various teams to enhance marketing performance and customer experience.

The DFT Design Engineering Architect will lead the DFT team and oversee the DFT insertion process from RTL to silicon debug. Responsibilities include scan chain insertion, MBIST, ATPG, debugging failures, and verification of testbenches, while collaborating with cross-functional teams.

The Application Engineer will identify and resolve technical issues in digital IC design, enhance design methodologies using Cadence tools, support evaluations of new EDA tools, and contribute to key design projects while collaborating with the sales team for opportunities.

The Sr Principal Product Engineer at Cadence will design and develop custom IC design flows, ensure technical specifications enhance software quality, support technical trainings, document design flows, and collaborate with global teams for technical solutions and customer engagement.

The Lead Software Engineer at Cadence will develop advanced Code Generation components, working on innovative projects while collaborating with cross-functional teams, including R&D, product validation, and customers. Key responsibilities include designing and implementing capabilities and generating sophisticated low-level C libraries.