Search the 102 jobs at Cadence Design Systems

The Principal Verification Engineer will be responsible for design verification in the IP development team, focusing on various Serial and Interface Design IPs. Responsibilities include developing UVM testbenches, conducting formal verification, participating in emulation qualification, and creating detailed verification strategies and test plans. Strong analytical skills and effective communication are essential for this role.

The Sr Solutions Engineer will develop Pegasus DRC/LVS runsets, automate regression tests, detect issues, and generate validation reports. They will also support customer tool bugs and enhancements, and collaborate with the R&D team.

The Senior Cloud Solution Engineer at Cadence is responsible for developing and maintaining cloud offerings, onboarding and supporting customers in the Cadence Managed Cloud portfolio. The role requires leveraging Linux and HPC on public cloud infrastructure, utilizing automation and infrastructure-as-code to ensure secure cloud environments and optimal customer support.

The Product Engineer II will develop Conformal expertise within regional teams, lead deployment of Conformal products, conduct training and seminars, capture customer feedback for tool enhancements, and collaborate with R&D to address customer issues. A strong background in ASIC implementation and programming skills in Tcl and Python is required.

The Sr. Principal Software Engineer will provide R&D support for customer-related issues, analyzing and fixing problems, as well as developing new features. The role requires significant problem-solving and innovative research in the EDA domain, with opportunities for mentoring in software engineering skills.

The Sr Principal Digital Verification Engineer will work on the architecture and management of verification environments for complex IP, develop self-checking regressions and functional coverage, and create automated regression environments while collaborating closely with design engineers.

The Senior Principal Design Engineer at Cadence is responsible for developing software for embedded processors and emulation platforms, focusing on efficient algorithms and data structures. The role demands strong programming skills in C/C++ and experience in firmware programming. Additionally, the engineer will collaborate with teams and customers while potentially engaging in international travel. A solid foundation in computer architecture and understanding of Neural Networks is beneficial.

As a Senior Account Technical Executive I, you will manage strategic accounts at Cadence, maximizing the value of their technology solutions, grow product adoption, and drive technical sales engagements. You will develop strategies, build relationships with stakeholders, and coordinate with internal teams to meet customer challenges and sales targets.

The Principal Design Engineer will lead design verification projects, ensuring complex designs are verified from concept to closure. Key responsibilities include environment planning, test plan generation, and developing functional verification environments using System Verilog and UVM.

As a Principal Design Engineer, you will be responsible for the verification of Serial and Interface Design IPs, utilizing UVM testbench development for efficient verification and participating in formal verification and emulation qualification. The role requires strong analytical, problem-solving skills, and effective communication capabilities.

The Sr Design Engineering Architect role involves RTL design for PCIe Architect with responsibilities in creating and supporting the RTL of PCIe/CXL/IDE/UALink IP solutions. The role requires significant expertise in various subsystems and ensures design compliance with verification guidelines.

As a Lead Design Engineer at Cadence, you will work on embedded processors, implement high-performance algorithms, and write/debug software for emulation platforms. You'll collaborate with diverse teams and customers to address issues while leveraging knowledge in Neural Networks and Deep Learning.

The Principal Design Engineer will lead major blocks of Memory PHY layout design, engaging in hands-on critical analog and high-speed layout blocks. Responsibilities include coordinating with circuit leads, layout contractors, and team members, as well as participating in layout reviews.

The Lead Software Engineer at Cadence will enhance software development for the Protium P&R tool, focusing on improving quality of results (QoR) and performance timing while collaborating with users to deploy new features. Candidates must have a strong background in software development and CS fundamentals.

The Principal Software Engineer at Cadence will leverage strong CS fundamentals to improve the quality of results (QoR) of the Protium Place & Route (P&R) tool. Responsibilities include enhancing P&R features for improved performance and collaborating with users to deploy tools effectively.

The Lead Solutions Engineer will review design specifications, develop verification strategies and test plans, and create constrained random verification environments. Responsibilities include writing functional tests and assertions to meet verification goals, with a focus on SOC verification using C-based test cases and various protocols.

The Lead Design Engineer at Cadence will develop firmware for various memory interfaces, collaborate with hardware designers and architects, deduce co-verification plans with the verification team, and support debugging efforts on simulations and silicon boards.

The Principal Design Engineer at Cadence is responsible for leading design verification projects, confirming complex designs are verified from concept to closure. This role requires extensive experience in functional verification fundamentals, test plan generation, and environment development using System Verilog and UVM.

The Principal Design Engineer is responsible for the integration, customization, and post-silicon bring-up of CDNS DDR IP subsystems. This role involves resolving complex implementation issues, supporting integration reviews, performing simulations for functionality, and enhancing customer communication and experience.

The Principal Design Engineer at Cadence will lead development in custom accelerator SoCs and collaborate with computational simulation teams. Responsibilities include designing verification processes, creating and maintaining test-benches, and participating in IP delivery and SoC tape-out. Candidates must have robust debugging skills and experience in a cross-team environment.