Jobs at Cadence Design Systems

Designs and maintains Eclipse-based IDE components, REST API servlets, web applications, database interfaces, and automated testing systems. Develops with Java, JavaScript, TypeScript, Python, React, SQL, and NoSQL databases across Windows and Linux. The engineer analyzes requirements, improves existing software, collaborates with hardware and architecture teams, and integrates Agentic AI workflows into developer tooling.

Design and implement high-performance SerDes physical IP: define digital architecture through micro-architecture and RTL, focus on low-power features, synthesis, timing, DFT, and verification collaboration. Execute tool flows and automation, work with mixed-signal, analog, verification teams, and apply embedded uC knowledge and AI-assisted design practices.

Partners with North America Sales to structure customer deals, evaluate pricing, discounts, revenue recognition, booking, fulfillment, and contract-term issues. Advises cross-functional quote-to-cash teams, resolves nonstandard deal risks, supports financial analysis and business model changes, and assists with post-acquisition integration. The role requires strong accounting knowledge, business acumen, communication, problem-solving, stakeholder influence, and attention to detail.

Lead semiconductor IP and foundry programs from initiation through delivery. Responsibilities include integrated scheduling, cross-functional engineering coordination, risk and dependency management, executive and customer reviews, governance, KPI reporting, stakeholder communication, resource tracking, and process improvement. The role aligns roadmaps, customer expectations, and execution plans while resolving complex delivery challenges across multiple engineering disciplines.

Lead architecture, development, and execution for Conformal logical equivalence checking and ECO technologies. Drive formal verification, scalability, performance, quality, debugging, and AI-powered innovation. Guide complex technical initiatives, resolve customer escalations, influence product strategy, collaborate across engineering and product teams, mentor senior engineers, and engage strategic semiconductor customers and partners.

Develops and validates Cadence’s Hardware Job Scheduler through software coding, bug analysis, performance profiling, requirements analysis, and integration. The role requires Python, Linux, version control, scripting, and communication in English and Portuguese. Preferred experience includes job scheduling tools, C++, distributed systems, multithreading, REST APIs, web development, and Verilog or VHDL.

Leads North American cloud business development, technical pre-sales, customer engagements, and go-to-market execution for Cadence’s EDA cloud solutions. Develops cloud product roadmaps, business models, and sales pipelines while collaborating with sales, IT, R&D, and ecosystem partners. Evangelizes AI-driven EDA tools and applies generative AI to improve customer interactions and pre-sales support. Translates customer and industry needs into cloud product strategies and business growth.

Perform product engineering for Cadence Genus synthesis software, validating new features and optimizing power, performance, and area for advanced ASICs. Solve physical-aware synthesis challenges, support field engineers and customers, verify interoperability with Cadence tools, gather requirements, document specifications, and provide root-cause analysis for complex logic, physical design, and timing-closure issues.

Characterize and validate analog and digital IP silicon solutions through post-silicon PHY, interoperability, compliance, and reliability testing. Lead and mentor engineers, coordinate with R&D and Marketing, develop automated lab tests, debug silicon failures, and analyze test results. Design high-speed PCB schematics and layouts, perform signal and power integrity analysis, and validate Ethernet, PCIe, CXL, or UCIe interfaces using advanced laboratory equipment.

Develop and maintain high-quality C/C++ code for HDL compiler and runtime support. Responsibilities include building compiler front-ends supporting SystemVerilog and VHDL language standards, improving compiler performance and infrastructure, and contributing to RTL simulation, synthesis, and runtime environments.

Leads customer-facing integration, customization, verification, and deployment of digital and mixed-signal IP subsystems. Supports SOC integration reviews, RTL and gate-level simulations, timing closure, DFT flows, package and board implementation, SI/PI reviews, and post-silicon bring-up. Acts as the primary interface between customers and R&D, manages technical cases and escalations, coordinates subject-matter experts, develops documentation, and uses AI tools to improve productivity and customer deliverables.

Design and verify high-speed, low-power analog mixed-signal SerDes transceivers for data-center, networking, AI, and HPC applications. Translate system requirements into circuit architectures, optimize performance across process and environmental conditions, develop behavioral models, collaborate on layout and signal integrity, and support tapeout, silicon bring-up, characterization, debugging, and production release.

Designs and develops reusable geometry, visualization, and simulation software components. Architects software components and APIs, implements multithreaded client-server applications, and maintains code quality across multiple products. Builds test automation, supports CI/CD and release automation with Azure Git Pipelines, and uses configuration management, build systems, debugging tools, and established development processes. Provides technical ownership and develops simulation software for Windows and Linux environments.

Supports the Lead Paralegal and Japan Legal Department with legal filing, document management, invoice processing, billing reconciliation, and tracking outside counsel payments. Reviews Anti-Corruption approval requests for completeness, follows up on pending items, and provides administrative assistance to attorneys and paralegals. The role also handles confidential information, special projects, and coordination with Finance and Accounts Payable.

Assist with regression reviews for Cadence Innovus place-and-route tools. Develop and maintain system infrastructure to improve productivity and efficiency using scripting and system development techniques. The internship requires at least four days per week for more than six months and involves digital backend flow, IC design, Unix systems, and scripting.

Assist with regression review for Cadence Innovus place-and-route tools. Develop and maintain system infrastructure to improve productivity and efficiency using scripting and system development techniques. The role requires digital IC design knowledge, Unix systems expertise, strong communication in English and Chinese, self-motivation, and a commitment to work at least four days weekly for more than six months.

On-site electrical engineering intern validating system-level and electrical performance of silicon test chips. Responsibilities include debugging silicon issues with analog and digital design teams, performing characterization and test automation, preparing reports, and supporting reliable product deployment. Requires strong fundamentals in analog and digital electronics, RTL, signal integrity, and control systems, plus analytical, communication, and teamwork skills.

Drive Cadence digital and signoff product support by applying RTL-to-GDSII, place-and-route, timing closure, and PPA optimization expertise. Collaborate with R&D, applications engineering, marketing, and release teams to resolve customer issues, conduct design benchmarks, and develop customer-specific flows and methodologies. Provide technical guidance on VLSI physical design, clock tree synthesis, routing, timing analysis, and silicon signoff at 7nm and below.

Leads advanced semiconductor signoff methodology development, customer enablement, product deployment, and technical investigations for timing, power, signal integrity, ECO closure, and physical implementation. Collaborates with customers, R&D, and field engineering teams to resolve design closure challenges, qualify advanced-node flows, support tapeouts, validate product enhancements, and influence roadmap direction. Provides technical leadership for strategic engagements, customer escalations, methodology collateral, and engineering mentorship.

Provide expert field applications engineering for digital implementation and signoff, guiding customers on Cadence synthesis, place-and-route, timing and power closure. Drive technical evaluations, demos, benchmarks, and tool adoption; collaborate with R&D to influence product direction and improve flows using scripting and best practices to meet PPA and design closure goals.