Jobs at Cadence Design Systems

Lead technical architect providing cross-project technical leadership and strategic direction. Make long-term architectural decisions, resolve complex design issues, drive processes and projects, mentor engineers, and partner with sales, accounts and executives to influence product strategy and customer outcomes.

Support and troubleshoot large-scale enterprise Linux and cloud infrastructure (AWS), identity/auth systems (LDAP, SSSD, PAM), and HPC schedulers (Slurm, LSF). Lead incident and problem management, produce migration plans, build lab simulations, perform performance tuning and root-cause analysis, collaborate with engineering/product/customers, document technical solutions, and drive operational improvements.

Lead physical implementation of high-speed DDR PHY IP: develop scripts/tools to improve PD flows, complete project tasks, resolve design issues, create preventive flows, and analyze/implement PPA optimization methodologies across advanced process nodes.

Lead Product Engineer driving STA timing-signoff product (Tempus) improvements: gather customer requirements, create detailed product specifications, collaborate with R&D, support tool deployment and enablement, and validate solutions using STA methodologies, SDC, and automation scripting.

Drive new business and grow strategic accounts by building pipeline, winning new logos, and managing complex enterprise sales cycles. Act as a technical, customer-facing advisor, collaborating with internal teams and partners to deliver solutions, analyze market trends, and expand territory revenue. Frequent travel required.

Design and implement high-performance SerDes physical IP: define digital architecture through micro-architecture and RTL, focus on low-power features, synthesis, timing, DFT, and verification collaboration. Execute tool flows and automation, work with mixed-signal, analog, verification teams, and apply embedded uC knowledge and AI-assisted design practices.

Lead Front End Design projects, mentor a team of RTL design engineers, develop microarchitectures, and oversee verification activities in the semiconductor industry.

Lead Physical Design projects and teams while collaborating with customers to meet performance targets and deliver complex SoCs. Drive innovation and technical solutions at advanced nodes, ensuring design closure and optimizing for power, area, and performance.

Develop and validate aeroelastic and aerothermoelastic simulation capabilities across low- to high-fidelity methods for subsonic through hypersonic flight. Implement numerical algorithms, multiphysics coupling (CFD-CSD, FSI), ROMs, and HPC-optimized solvers. Collaborate with structural dynamics, CFD, and product teams to transition research into commercial software, support customer demonstrations, and participate in verification, validation, and CI workflows.

Work as an R&D software engineering intern on Jasper formal verification tools: implement bug fixes and features, write C++ (OOP) on Linux, script flows (Tcl/Python), implement algorithms/data structures, and collaborate on test creation and QA regression.

Manage employee onboarding, offboarding, and lifecycle administration; maintain HR records and compliance with China labor regulations; coordinate hukou and work/ residence permit processes; serve as first point of contact for HR inquiries; support employee engagement events and HR projects.

Develop assertion-based verification IPs: implement Verilog models and SystemVerilog assertions for standard bus protocols, create scripts/automation (Python/TCL), apply verification methodology, generate test plans and coverage, debug using EDA tools, and coordinate with cross-geography teams. Strong RTL/synthesis and protocol knowledge required; formal verification and AI-tool exposure are beneficial.

Partner with semiconductor customers to drive RTL-to-GDSII implementation on advanced nodes, develop methodologies, debug tool issues, deploy ML productivity solutions, influence product direction, collaborate with sales and mentor AE teams.

Provide technical support for digital IC backend implementation. Require strong RTL-to-GDSII methodology knowledge and practical experience in floorplanning, placement, CTS, routing, STA timing closure, physical verification, RC extraction, and power network analysis. Serve as a team lead on routine and general assignments, with scripting and programming skills required.

The role involves collaborating with R&D and Application Engineering teams to enhance chip design tools, focusing on PPA benchmarking and optimization.

Partner with HR, Legal, Finance, Marketing to identify and prioritize back-office improvements; design, prototype, test, and deploy practical solutions (process fixes, automations, AI workflows, agentic systems); work with IT for access and handoff; document logic and assumptions; communicate progress and tradeoffs while prioritizing business impact and maintainability.

Lead deployment of Portable Stimulus methodologies for complex SoC verification. Debug generation/solver and modeling challenges, collaborate with Cadence R&D, develop reference models and best practices, support software-driven verification, reuse across simulation/emulation/post-silicon, and contribute to AI-assisted verification workflows.

The Principal Product Engineer will develop innovative characterization solutions for foundational IPs, engage with customers, and drive product adoption efforts.

Lead cross-functional teams to deliver complex services and technology engagements for external customers. Manage project lifecycle, schedules, budgets, risks, resources, and stakeholder communications while collaborating with sales and engineering teams.

Lead firmware architecture, implementation, verification, and validation for high-speed Die-2-Die and UCIe PHY IPs. Develop prototype control software, validate in emulation and simulation, support post-silicon electrical/system characterization, debug customer deployments, provide hot fixes, and maintain firmware documentation.