The engineer will develop DFT tools, enhance usability, and support R&D activities, focusing on RTL design and verification.

The Principal Design Engineer will manage design verification for interconnect IP, craft and execute verification plans, and collaborate with cross-functional teams.

The role involves performing static timing analysis, glitch and noise analysis, automation of flows, and technical training with extensive experience in timing analysis methodologies.

Manage and optimize OpenStack and Nutanix environments, ensuring high availability, scalability, and compliance while collaborating across teams and documenting processes.

Develop and maintain AI applications in digital verification. Lead design, analysis, and implementation of AI algorithms while ensuring high software quality through collaboration and code reviews.

As a Software Engineer II, you will develop ML functionalities, optimize solutions, solve computational problems, and collaborate globally on impactful projects.

Develop performance models for DDR memory controller architectures, perform architectural analysis, and automate performance metrics generation.

The role involves designing verification strategies for IP development, focusing on functional and formal verification of various digital interface IPs using UVM testbenches.

The Principal Digital Design Engineer will develop high-performance physical IP, contribute to digital architecture and RTL, and coordinate with multiple teams for project execution.

Responsible for power design and hardware system platform sustainment. Works with mechanical teams on power delivery and collaborates with vendors for PDU and PSU design.

The Principal Analog IC Designer focuses on designing and developing analog/mixed signal ICs, particularly for long-reach SerDes, requiring extensive experience in high-speed I/O ICs and proficiency in CAD tools.

The role involves supporting compliance operations, conducting audits, customer screenings, managing IT for compliance programs, and ensuring adherence to global trade standards.

The Lead Applications Engineer will architect memory solutions, provide technical presales support, present IP portfolio to customers, and evaluate performance of memory IP.

The Principal Solutions Engineer leads projects, collaborates with teams, scopes customer projects, develops methodologies, and trains customers on analog layout implementation challenges. A deep understanding of IC layout, physical implementation, and automation is essential.

The Lead Engineer will be responsible for testing and characterizing high-speed SerDes IPs, developing software scripts, generating reports, and collaborating with the R&D team.

The Application Engineer II role involves providing technical support for Cadence's verification products, focusing on hardware emulation and prototyping, and innovating solutions to customer challenges.

Lead the verification of VIP using Verilog/SystemVerilog/UVM, manage a small team, and interact with customers. Requires strong technical skills and communication abilities.

The Principal Product Engineer will bridge customers and R&D, develop verification solutions, and deliver new features, requiring strong technical skills and customer collaboration.

The Application Engineer supports customers in using EDA tools for IC design, delivers training and technical presentations, and facilitates the integration of Cadence solutions into production flows.

Support silicon bring-up and debug of Memory IP subsystems, ensure integration of Memory PHY and Controller IP into customer systems, and collaborate with cross-functional teams to solve technical issues.