The role involves developing verification plans for SOCs, executing verification methodologies, addressing debug issues, and collaborating with engineering teams.

The Lead Design Engineer will execute verification plans for SOC and IP blocks, ensuring testability while collaborating with design and verification teams.

Searching for a VLSI Design Verification Engineer with 3-5 years of experience to develop and execute verification plans for SOC projects, ensuring testability and design intent.

Seeking an experienced SOC Design engineer with expertise in protocols and design verification to collaborate with internal teams and customers.

The Lead Design Engineer will design and implement SOC designs, collaborating with teams and ensuring verification, testability, and addressing complex issues.

The Lead Application Engineer will work with Sales to scope solutions, manage technical evaluations, conduct trainings, and provide client support. Expertise in design and verification needed.

Seeking a Lead Software Engineer with expertise in HDLs and experience in EDA tools and functional verification of digital systems.

The Account Technical Executive will lead technical campaigns in the semiconductor industry, focusing on customer challenges and system-level solutions.

The Principal Design Engineer leads the Functional Safety Design Verification Team, developing and verifying safety mechanisms in hardware and software for Xtensa processors, while ensuring compliance with safety standards.

Cadence is offering a 16-week paid returnship for Physical Design Application Engineers to update skills and re-enter the workforce after caregiving. Candidates will work with EDA tools on Digital Synthesis, Place and Route, and Signoff Analysis.

The Lead Applications Engineer will architect memory solutions, provide technical presales support, present IP portfolio to customers, and evaluate performance of memory IP.

The Sr. Principal Analog IC Designer designs and develops analog/mixed-signal ICs, focusing on SerDes architecture, circuit performance, and provides leadership to junior designers.

Drive RTL-to-GDSII metrics, engage in solution-driven discussions, and implement ML solutions to enhance productivity and design outcomes.

Develop and maintain a constraint solving engine, analyze requirements, propose solutions, and collaborate with team members and customers globally.

The PDK Enablement Engineering Specialist supports circuit implementation teams by managing foundry files and tools, ensuring quality and efficiency in semiconductor design.

As an Application Engineering Intern, you'll support the Silicon Signoff and Verification team, assist customers in adopting solutions, and contribute to technical evaluations, presentations, and training.

The role involves writing designs in Verilog/System Verilog/C/C++/TCL for testing, validation of features on Protium, hands-on debugging, and collaboration with the development team.

The Software Engineer I will integrate silicon and firmware, conduct post-silicon tests, and develop validation automation for complex systems.

The Software Engineer II will develop Cadence’s verification tools, working within a team to create high-quality software solutions while adhering to coding standards.

The Senior Design Manager will lead SOC design teams, oversee design processes including RTL and integration, and manage project schedules while improving productivity and quality.