Jobs at Cadence Design Systems

Architects and designs configurable RTL solutions for DDR controller features and customer requirements. Develops high-speed circuits, low-power capabilities, and SoC architecture while collaborating with verification, support, delivery, applications, and PHY teams. Uses design automation and IP development tools, improves engineering processes through automation, and provides technical team leadership.

Support configuration management for a large-scale software product and engineering organization. Manage source control, build and test infrastructure, SCM processes, scripting, and UNIX environments across thousands of machines and millions of tests. Collaborate on complex projects and operational requests while troubleshooting issues and learning new technologies. Preferred experience includes web technologies, databases, and software analysis tools.

Lead ASIC physical design implementation from floorplanning and power-grid design through place and route, clock-tree synthesis, timing closure, signal integrity, physical verification, EM/IR signoff, and DFM closure. Develop physical design methodologies and flows, collaborate with RTL teams on tapeouts, and independently verify, test, and characterize designs across advanced technology nodes.

Lead and execute ASIC physical design implementation, including floorplanning, power grid design, place and route, clock tree synthesis, timing closure, signal and power integrity, physical verification, EM/IR signoff, and DFM closure. Develop physical design methodologies and flows, work on advanced low-power and high-speed designs, collaborate with RTL teams, and support successful tapeouts.

Supports Cadence digital implementation and signoff products, troubleshoots customer issues with R&D and release teams, runs design benchmarks, and develops implementation flows and solutions. Provides expertise in ASIC RTL-to-GDSII methodologies, timing closure, PPA optimization, physical design, routing, clock tree synthesis, and silicon signoff for advanced process nodes.

Supports Cadence verification products through customer opportunity scoping, technical evaluations, benchmarking, training, demonstrations, and issue resolution. Partners with sales, marketing, corporate engineering, customers, and business units to understand requirements and improve product direction. The role requires knowledge of Linux and Tcl, familiarity with simulators and emulation platforms, strong communication, engagement management, teamwork, and unrestricted international travel availability.

Six-month internship focused on completing a digital RTL-to-GDSII implementation flow using Cadence tools and InnoStack, an AI-powered engineering assistant. Responsibilities include generating scripts and methodologies, running and optimizing implementation stages, analyzing reports, troubleshooting technical issues, validating AI recommendations, and delivering a fabrication-ready database. The intern will also document prompts, best practices, limitations, and lessons learned in an InnoStack Experience Roadbook.

Architects and designs processor core logic enhancements in partnership with the Chief Architect. Collaborates with validation and physical design teams to productize solutions, focusing on areas such as load/store, instruction fetch, branch prediction, memory management, and bus protocols. The role may also analyze performance bottlenecks, model improvements, and implement optimization solutions.

Collaborate with R&D teams to track CCRs, product releases, and special software branches. The role supports program coordination and delivery within a technology-focused environment.

Supports Cadence digital implementation and signoff products by debugging customer issues, partnering with R&D and release teams, running design benchmarks, and developing implementation flows. Requires deep expertise in ASIC RTL-to-GDSII methodologies, timing closure, PPA optimization, physical design, low-power and hierarchical design, and industry-standard EDA tools. The role also involves automation using Perl, Tcl, and shell scripting.

Develop and validate software for physical verification of advanced semiconductor devices. Solve complex mathematical and geometric problems, maintain reliable engineering applications, collaborate with global R&D teams, participate in code reviews, and improve development processes for next-generation chip design and manufacturing technologies.

Develop compiler software for the Cadence Palladium emulation platform, solving large-scale compilation problems through logic optimization, distributed databases, precompilers, multithreading, and distributed computing. Responsibilities require strong data structures, algorithms, database, C++ development, debugging, and Linux/Unix skills, with exposure to hardware description languages and electronic design platforms.

Develop compiler technology for the Cadence Palladium emulation platform. Responsibilities include solving large-scale compilation problems involving logic optimization, distributed computing, multithreading, distributed databases, and precompiler technologies. The role requires strong software engineering, data structures, algorithms, C/C++ programming, debugging, and Linux/Unix development skills, along with familiarity with hardware description languages and electronic design platforms.

Internship introducing SoC system-level validation and automation. The intern will use Cadence Incisive and Palladium tools to create, run, debug, and analyze pre-silicon system-level tests, while learning IC design methodologies, validation workflows, and chiplet development in a global engineering team.

Interns will contribute to Virtuoso and AWR electronic design automation product development. Responsibilities include learning RF design analysis and implementation tools, software development processes, algorithm design and analysis, software debugging, GUI development, and developing product features for customers.

Software Engineering Intern supporting Cadence’s Quantus Insight R&D team. The intern will develop product features, investigate large-scale data and performance problems, participate in design reviews, debugging, testing, and code reviews, and explore automation and AI-driven workflows. Candidates should have programming experience, strong analytical and problem-solving skills, knowledge of algorithms and data structures, and effective communication and teamwork abilities. Modern C++, Linux, GUI development, multithreading, and EDA knowledge are beneficial but not required.

Supports testing and validation of Cadence Pegasus physical verification flows, develops verification test cases, analyzes results, investigates and reproduces issues, and assists with debugging. The intern also helps qualify semiconductor process technologies, creates automation scripts, prepares technical documentation, and collaborates with global Product Engineering, R&D, and customer teams.

This internship introduces analog and digital IC design for high-speed communication circuits. The intern will use Cadence Spectre SPICE and Virtuoso tools to design and implement basic IC circuits, contribute to mixed-signal IC product development, participate in team meetings, and learn industry design methodologies. The role requires enrollment in a Bachelor’s or Master’s program in Electrical and Electronic Engineering and an interest in IC design, signal processing, telecommunications, and control theory.

Interns will contribute to Virtuoso product development, gaining experience in RF design analysis, software development, algorithm design and analysis, debugging, GUI development, and software development processes. The role supports next-generation electronic design automation products and features for major customers while working within a collaborative, global engineering organization.

Develop Python automation tools and AI-powered applications using LLMs, agentic AI, APIs, and web technologies. Analyze workflows, prototype solutions for content intelligence and knowledge management, and collaborate with engineers and technical writers to improve productivity through process automation.