Jobs at Cadence Design Systems

Researches, designs, and develops efficient mesh-generation and computational-geometry algorithms for complex 2D and 3D models. Improves mesh quality, robustness, and performance; resolves geometric, topological, and numerical issues; and optimizes code through parallel computing and multithreading. Collaborates on technology integration and contributes to testing, debugging, code reviews, documentation, and AI-assisted development.

Administer and troubleshoot Windows and Linux servers, VMware environments, networks, storage, data center infrastructure, and core services. Build development and QA environments, manage Jenkins infrastructure, automate configuration with Bash, Python, and PowerShell, and support engineering workstations. Lead incident response, disaster recovery, patching, upgrades, infrastructure changes, vendor coordination, hardware procurement, documentation, and operational handovers while maintaining reliable business-critical systems.

Validates accounts, creates and approves business partners, enters orders in EDAOnTap, follows up on license delivery, distributes invoices, extends licenses after payment collection, handles operational queries, performs export compliance checks, and supports ad hoc requests.

Validate, improve, and regress Cadence’s Tempus signoff ECO solution. Develop product flows, define test methodologies, automate processes, and improve quality and performance. Collaborate with R&D, product engineering, and release teams to define specifications and address customer needs. Apply expertise in static timing analysis, signal integrity, timing and power closure, ECO workflows, physical design tools, Verilog, and scripting.

Internship opportunity at Cadence focused on developing future leaders and innovators in technology. The specific responsibilities and qualifications are not provided.

Lead static timing analysis and ECO signoff campaigns using Cadence Tempus. Develop and validate timing, correlation, constraints, and automation flows; benchmark tool features; collaborate with R&D and customers on advanced technology designs; support physical design concepts; resolve tool issues; and deliver technical training and seminars.

Provides pre-sales and post-sales technical support for Cadence digital implementation and signoff tools. Delivers customer workshops, benchmarks, demonstrations, methodology consultations, technical evaluations, and product support. Partners with sales teams on technical campaigns, supports customer implementations and usage expansion, collaborates with R&D on methodology improvements, and creates technical content. Requires expertise in digital design, semiconductor fundamentals, static timing analysis, ASIC implementation flows, scripting, and customer-facing problem solving.

Serves as a senior technical leader for Cadence’s field applications team, guiding semiconductor customers in adopting digital implementation, signoff, and Agentic AI solutions at advanced nodes. Leads technical engagement strategies, benchmarks, flow optimization, design closure initiatives, and customer escalations. Collaborates with R&D and product engineering, influences tool enhancements, leads technical teams, and represents Cadence through industry presentations and technical publications.

Provides customer-facing technical expertise for digital IC implementation and signoff using Cadence technologies. Deploys PPA methodologies, leads technical evaluations, supports synthesis, place-and-route, timing and power signoff, guides customers toward design and schedule goals, and collaborates with R&D to improve tools and flows. The role requires extensive hands-on digital design experience, advanced-node expertise, scripting proficiency, and strong communication skills.

Develop AVIP and Virtual Bridge solutions, improve software stack performance, create QEMU-based device models, apply AI methods to debugging flows, optimize GSFIFO technology with the ixcom team, and collaborate with customers on requirements and next-generation AVIP protocol architecture.

Leads advanced-node digital IC implementation engagements across pre-sales and post-sales customer projects. Drives synthesis, place-and-route, clock-tree synthesis, floor planning, timing closure, signoff, and power optimization at 3nm and below. Develops TCL, Perl, and Python automation solutions, resolves complex design issues, partners with sales, and mentors engineers. Requires extensive physical implementation experience, multiple tapeouts, strong communication, and technical leadership.

Owns enterprise endpoint security architecture and strategy across Windows, Linux, and macOS. Designs and governs EDR/XDR capabilities, integrations, security standards, detection and response controls, endpoint hardening, automation, and Zero Trust alignment. Provides technical leadership during investigations, transformations, mergers and acquisitions, technology evaluations, audits, and architecture reviews while mentoring engineering teams and advising executives.

Provides technical leadership and customer application support for Cadence advanced packaging and 3D-IC solutions. Develops workflows, demonstrations, proof-of-concepts, signoff methodologies, reference flows, and training for 2.5D/3D-IC, chiplet, substrate, interposer, and AI/HPC packaging. Supports customer evaluations and deployments, collaborates with sales on pre-sales engagements, communicates requirements to R&D, and advises on signal integrity, power integrity, thermal analysis, and package design.

Manage the full lifecycle of advanced process core IP development projects and customer engagements. Plan schedules, milestones, resources, budgets, risks, changes, quality, documentation, and delivery. Coordinate cross-functional teams, communicate with stakeholders, manage customer relationships, resolve issues, and drive continuous process improvement using AI/ML and other innovative methods.

Six-month internship applying AI, automation, and Python-based tools to semiconductor ATE test development and debugging. The intern will analyze test methods, logs, and results; develop prototypes for anomaly detection, root-cause analysis, and workflow improvement; validate solutions using real semiconductor test cases; document findings; and present recommendations to test engineers.

The role focuses on driving customer engagement, developing business strategies, supporting cloud products, managing partnerships, and coordinating with stakeholders to enhance Cadence's cloud business.

Develop verification and emulation environments for complex chiplet designs. Create UVM-SystemVerilog scoreboards, functional coverage, assertions, formal and simulation environments, and automated regressions. Integrate Cadence verification and accelerated VIP, manage verification plans in vManager, and collaborate with architects and design engineers to debug complex scenarios. Participate in technical and ISO-9001 checklist reviews.

Plans and manages technical evaluations of Cadence functional logic verification solutions with customers and R&D. Provides customer training, presentations, demos, project support, technical expertise, and team ramp-up on advanced verification technologies. Requires hands-on RTL design and verification experience using HDL simulators, Verilog, SystemVerilog, VHDL, or SystemC, plus knowledge of protocols, UVM, coverage, VIPs, and performance optimization.

Provides technical presales, configuration, demonstrations, and customer support for Cadence high-speed SerDes interface IP. Presents IP capabilities, serves as a protocol and product expert, collaborates with sales, marketing, and R&D teams, supports customer opportunities, leads productivity initiatives, and creates technical content. Requires expertise in high-speed protocols including PCIe, CXL, Ethernet, or USB, along with strong presentation and communication skills.

Manage Cadence’s academic programs, university partnerships, student innovation initiatives, and workforce development activities. Lead program timelines, budgets, documentation, communications, dashboards, reporting, onboarding, and engagement across key universities. Develop marketing content and communication strategies, coordinate conferences and academic events, support speakers and participants, and track participation, outreach, and program outcomes. Partner with Corporate Marketing and internal stakeholders to expand Cadence’s academic ecosystem and promote emerging technologies such as Physical AI and semiconductor design.