Jobs at Cadence Design Systems

Supports Cadence product adoption and customer RTL-to-GDSII implementation projects. Performs synthesis, place and route, clock tree synthesis, static timing analysis, low-power and multi-voltage implementation, timing debugging, tapeout support, and full-flow methodology development. Leads customer evaluations, competitive benchmarks, technical presentations, and implementation services across advanced technology nodes for complex CPU, GPU, DSP, wireless, and mobile designs.

Lead static timing analysis and timing closure for advanced-node SoCs. Responsibilities include debugging setup and hold violations, signal integrity and variation issues; driving PPA optimization through timing ECOs; correlating STA with SPICE; supporting foundry enablement for 5nm, 3nm, and 2nm nodes; collaborating with physical design, CAD, and foundry teams; and developing Tcl/Python automation for signoff workflows.

Leads global HR strategy and serves as a strategic partner to executive and leadership teams. Responsibilities include organizational design, workforce planning, succession, talent reviews, performance and compensation processes, employee relations, change management, and support for reorganizations and acquisitions. Uses workforce insights to identify risks and capability gaps, coordinates regional HR teams and Centers of Excellence, facilitates leadership discussions, and develops HR talent.

Designs custom analog and mixed-signal IC layouts, including floorplanning, matching, routing, hierarchy, and noise reduction for high-speed PHYs such as SerDes, USB, and DDR. Collaborates with analog circuit designers and digital place-and-route teams. Performs DRC, LVS, ERC, and EMIR analysis using industry layout verification tools, recommends solutions, and supports advanced-node and FinFET designs.

Develop firmware for high-speed SERDES physical-layer IP throughout architecture, implementation, verification, validation, post-silicon testing, and customer deployment. Responsibilities include building prototype control software, implementing adaptation and equalization algorithms, supporting FuSa-compliant testing, debugging hardware and firmware issues, delivering hot fixes, and maintaining technical documentation.

Develop firmware for high-speed SERDES physical-layer IP across architecture, implementation, verification, validation, silicon bring-up, debugging, and customer deployment. Build prototype control software for adaptation, equalization, and control algorithms; support functional-safety compliance, post-silicon characterization, issue resolution, hot fixes, testing, and technical documentation. Collaborate with digital and mixed-signal architects, verification teams, validation engineers, product engineering, and customers.

Manage end-to-end recruitment for niche semiconductor, VLSI, and EDA engineering roles. Responsibilities include partnering with hiring managers, sourcing active and passive candidates, screening technical talent, building talent maps, providing market intelligence, coordinating interviews, negotiating offers, maintaining ATS data, and tracking recruiting metrics. The role supports senior, niche, and high-volume hiring while ensuring strong candidate engagement and stakeholder communication.

Develop firmware for high-speed SERDES physical-layer IP across architecture, implementation, verification, testing, silicon validation, and customer deployment. Collaborate with digital and mixed-signal architects, build prototype control software for adaptation and equalization algorithms, support functional-safety compliance, debug hardware and firmware issues, deliver customer hot fixes, and maintain technical documentation.

Supports Cadence verification products through customer technical evaluations, benchmarks, trainings, demonstrations, debugging, and project ramp-up. Partners with sales, marketing, and corporate engineering to address customer requirements and guide product improvements. Requires expertise in verification, prototyping, EDA-based consumer application design, simulators, emulation or acceleration platforms, Linux, Tcl, and strong customer engagement skills.

Supports HR People Operations and Talent Acquisition through recruiting coordination, candidate and hiring manager follow-up, onboarding, documentation, benefits administration, employee records, vacation and time tracking support, and maintenance of HR systems and files. Provides general administrative assistance to employees and interns. Requires a bachelor's degree or equivalent, prior HR experience, and fluency in English and Portuguese.

Develop and validate Cadence Hardware Job Scheduler software using C++ and Python. Responsibilities include feature design, customer issue troubleshooting, bug fixing, DevOps activities, build and release deployment, product validation, and documentation. The role also involves analyzing requirements and collaborating on scheduling, distributed systems, debugging, and hardware emulation capabilities.

Design, build, and maintain infrastructure automation using Terraform, Ansible, Python and Bash; manage virtualization (Nutanix, KVM, VMware); build CI/CD pipelines; support hybrid cloud (AWS/Azure); monitor observability; ensure security/compliance; mentor junior engineers.

Lead cross-functional teams delivering complex customer services engagements and technology initiatives from initiation through completion. Manage project plans, schedules, budgets, resources, risks, milestones, and performance reporting while coordinating with engineering, sales, field, services, customers, and executives. Drive specialized engineering projects, resolve issues, ensure technical and commercial accountability, and maintain high customer satisfaction. Occasional domestic and international travel is required.

Support and optimize Linux-based on-premises and cloud compute farms, including system upgrades, workload migrations, acceptance testing, storage, networking, and troubleshooting. Automate repetitive tasks, improve resource utilization and user productivity, provide farm and systems expertise, and collaborate with global R&D and IT teams on infrastructure and technology initiatives.

Supports Linux-based on-premises and cloud compute farms, including system upgrades, workload migrations, acceptance testing, maintenance, troubleshooting, storage, networking, and performance optimization. Automates recurring tasks, improves resource utilization, supports R&D users, and collaborates with global IT teams on infrastructure improvements and knowledge transfer.

Provides technical support to customers using Cadence digital design and signoff tools. Collaborates with customer engineering teams to investigate issues, develop solution tests, deliver resolutions, and create technical documentation. The role focuses on RTL, synthesis, place-and-route, signoff timing, IC front-end and back-end flows, scripting, logic design, and customer enablement.

Researches, designs, and develops efficient mesh-generation and computational-geometry algorithms for complex 2D and 3D models. Improves mesh quality, robustness, and performance; resolves geometric, topological, and numerical issues; and optimizes code through parallel computing and multithreading. Collaborates on technology integration and contributes to testing, debugging, code reviews, documentation, and AI-assisted development.

Lead static timing analysis and timing closure for advanced SoCs across block and full-chip designs. Debug setup/hold, signal integrity, variation, and correlation issues; execute physical-aware ECOs; optimize PPA; support advanced-node and foundry enablement; and automate timing workflows with Tcl and Python. Collaborate with R&D, physical design, CAD, and foundry teams while contributing to AI-enabled signoff methodologies.

Develop and improve software in C or C++ on Linux, applying data structures, algorithms, debugging, testing, and software engineering principles. The role involves using and validating coding agents for repository exploration, implementation, testing, debugging, and documentation. Preferred work includes performance engineering, parallel programming, systems programming, electronic design automation, and modern development workflows with build systems, version control, automated testing, and objective validation.

Develop and optimize audio codec and audio-processing firmware for Tensilica HiFi embedded DSP processors. Responsibilities include C and assembly development, performance tuning, firmware feature and interface updates, documentation, and resolving audio issues with internal engineering teams and partners. The role requires expertise in DSP audio and speech processing standards, embedded hardware, software and interface design, and independent technical collaboration.