Jobs at Bolt Graphics

Lead end-to-end hardware system architecture for graphics compute platforms, GPU servers, and PCIe graphics products. Define physical topologies, high-speed interconnects, PCB stackups, power delivery, thermal integration, and management infrastructure. Lead JDM/ODM engineering partners through design reviews, bring-up, signal and power integrity validation, failure analysis, DFX compliance, and transition from EVT/DVT to high-volume manufacturing.

Manages graphics engineering programs, schedules, deliverables, global team coordination, risk mitigation, stakeholder reporting, and project-management process improvements. Serves as the primary internal contact for graphics software development programs while balancing product goals, delivery speed, and competing priorities. Requires close collaboration with engineers, executives, and technical and non-technical teams. The role is onsite in the Bay Area three to four days weekly with occasional travel.

Oversee workplace and facilities operations across Sunnyvale, Taiwan, and future locations. Manage maintenance, vendors, budgets, supplies, food programs, safety compliance, inspections, logistics, shipping, hotel reservations, and company apartment upkeep. Coordinate contractors and local teams, establish consistent operational standards, support employee and guest experience, and ensure safe, organized, well-maintained workplaces.

Serve as the technical counterpart to the commercial team for HPC and computational engineering customers. Lead workload discovery, performance analysis, benchmarking, proofs of concept, technical evaluations, and deployment planning. Translate customer needs into engineering requirements, explain Bolt’s GPU architecture, resolve technical blockers, develop technical materials, and assess technical fit. Support strategic partners, national laboratories, government organizations, and industry events while bringing customer feedback into product strategy.

Own end-to-end hardware system architecture for graphics compute platforms, GPU servers, and PCIe graphics form factors. Define physical topologies, high-speed interconnects, PCB stack-ups, power delivery, telemetry, and management infrastructure. Lead JDM/ODM engineering partners through layout, bring-up, validation, debug, failure analysis, DFX reviews, and high-volume manufacturing. Collaborate across silicon, signal and power integrity, thermal, and mechanical engineering teams to deliver high-performance graphics hardware.

The RTL Design / Microarchitecture Engineer will define and implement microarchitectural components, optimize performance, and collaborate with cross-functional teams.

As a Principal Design Verification Engineer, you will lead verification strategies and teams for complex IPs or full-chip SoCs, ensuring high-quality silicon delivery through comprehensive verification methodologies and cross-functional collaboration.

Responsible for full-chip or block-level physical design from netlist to GDSII, ensuring timing, power, and area targets are met. Collaborates with teams for design convergence and performs DRC/LVS/EM/IR debugging.

The Site Reliability Engineer will design, implement, and manage reliable infrastructure and services, ensuring operational excellence and uptime.

The Senior Design Verification Engineer develops and verifies silicon IP, optimizing and characterizing performance using advanced tools, while leading a team.

Lead end-to-end ASIC physical implementation from netlist to GDSII, covering synthesis support, floorplanning, placement, CTS, routing, signoff, timing closure across corners, ECO flows, physical verification (DRC/LVS/EM/IR), integrating hard macros, and automating PD flows with TCL/Python while collaborating with RTL, verification, and foundry teams to meet PPA targets.

Design and implement RTL and microarchitectural components for high-performance SoC/IP. Develop SystemVerilog/Verilog modules, optimize PPA, collaborate with verification and physical design teams, support IP integration and silicon bring-up, and contribute to documentation and methodology improvements.

Lead development, optimization, and verification of digital silicon IP. Create and maintain specifications and documentation. Characterize IP performance using FPGA simulation and emulation and collaborate with architecture, PD, and software teams from design through bring-up.

Lead SoC architecture definition for next-generation compute platforms. Drive tradeoffs across performance, power, area, bandwidth and latency; define memory hierarchy, NoC/interconnect, coherency, and subsystem partitioning. Lead performance modeling and workload analysis (C/C++/SystemC), integrate third-party IPs, collaborate with RTL, verification, physical design, firmware and software teams, support silicon bring-up, debugging, validation and roadmap planning.

Lead architecture definition and technical direction for next-generation GPUs. Define data-parallel microarchitecture and memory/coherency hierarchies, drive tradeoffs (performance/power/area), perform workload profiling and performance modeling, collaborate across RTL/verification/physical/firmware/software teams, support silicon bring-up and post-silicon tuning, and contribute to long-term roadmap planning.

Plan and oversee low-level software and driver development for graphics processors. Manage schedules, risks, deliverables, and cross-team coordination; report progress to stakeholders; improve PM processes; coordinate with other PMs; communicate closely with engineers and executives. On-site 3-4 days/week in the Bay Area with occasional travel.

Lead enterprise master data architecture and PLM implementation, design item master and lifecycle schemas, build data quality and ETL pipelines, integrate CAD/EDA and PLM with ERP/MES, oversee data governance, BOM audits, and supply-chain data syndication for high-volume semiconductor manufacturing.

Plan and oversee SoC/IC chip design programs, manage schedules and risks, coordinate global teams and other PMs, report progress to stakeholders, and improve PM processes to meet product goals.

The role involves leading architecture definition for next-gen GPUs, driving performance modeling, integration, and collaboration across multiple teams. Responsibilities include defining microarchitecture, optimizing performance, and supporting silicon bring-up while contributing to product roadmap planning.

Lead Philippines finance and operations: manage GL/AP/AR, month/quarter/year-end close, inventory/COGS and equipment depreciation, prepare PFRS/IFRS financial statements, ensure BIR/SEC tax compliance and filings, handle audits, design SOPs and internal controls, leverage NetSuite/cloud ERP to automate reporting and support cross-functional budgeting and inventory tracking for a distributed team.