Jobs at Bolt Graphics

Owns ERP platform selection, implementation, configuration, integrations, data governance, reporting, and continuous improvement. Ensures accurate manufacturing, supply chain, inventory, costing, procurement, and financial data across ERP, PLM, MES, and external partners. Leads system administration, release management, user enablement, data quality controls, audits, and cross-functional governance while supporting production scale and financial compliance.

Own the enterprise master data architecture and PLM strategy across engineering, supply chain, finance, and manufacturing. Design item master schemas, governance standards, data-quality controls, and digital-thread integrations. Lead PLM platform selection, implementation, migration, workflow configuration, and PLM-to-ERP connectivity. Establish supply-chain data syndication, BOM audits, and compliance processes. The role requires strong hardware development, EDA, CAD, systems integration, ETL, SQL, and data governance expertise, plus cross-functional technical leadership.

Develop executable models, simulations, and analytical workflows for semiconductor SoC and IP systems. Define ASIC system requirements, translate system requirements into block- and circuit-level specifications, and analyze microarchitecture trade-offs involving interconnects, caches, memory controllers, and coherency. Collaborate with product management, architecture, and SoC design teams to establish performance, power, and area targets. Improve modeling methodologies, support model-driven design, and correlate pre-silicon models with post-silicon performance.

Plan and oversee SoC/IC chip design programs, manage schedules and risks, coordinate global teams and other PMs, report progress to stakeholders, and improve PM processes to meet product goals.

Develop executable models, simulations, and analytical workflows for SoC and IP systems. Define ASIC requirements, translate system specifications into block- and circuit-level designs, analyze microarchitecture trade-offs across performance, power, and area, and collaborate with product, architecture, and SoC design teams. Improve modeling methodologies, support model-driven design, and correlate pre-silicon models with post-silicon performance.

The Controller owns accounting operations, financial reporting, monthly and annual close, GAAP compliance, internal controls, audits, tax support, and equity compensation accounting. The role administers QuickBooks and Carta, supervises accounting staff, improves finance systems and processes, supports budgeting and forecasting, and prepares investor and board reporting. The Controller also partners with auditors, tax advisors, legal counsel, and executives while building scalable finance operations for a growing semiconductor startup.

Lead product definition, system architecture, and lifecycle execution for PCIe accelerator cards and 2U HPC servers. Own hardware requirements, memory and networking strategy, thermal and power trade-offs, silicon-to-system validation, NPI, mass production, ODM/EMS partnerships, BOM optimization, and hardware ecosystem development. The role requires expertise in high-speed PCIe design, DDR5/LPDDR5X or HBM memory, embedded processors, Linux, high-bandwidth networking, and post-tape-out hardware delivery.

Lead end-to-end hardware system architecture for graphics compute platforms, GPU servers, and PCIe graphics products. Define physical topologies, high-speed interconnects, PCB stackups, power delivery, thermal integration, and management infrastructure. Lead JDM/ODM engineering partners through design reviews, bring-up, signal and power integrity validation, failure analysis, DFX compliance, and transition from EVT/DVT to high-volume manufacturing.

Serve as the technical counterpart to the commercial team for HPC and computational engineering customers. Lead workload discovery, performance analysis, benchmarking, proofs of concept, technical evaluations, and deployment planning. Translate customer needs into engineering requirements, explain Bolt’s GPU architecture, resolve technical blockers, develop technical materials, and assess technical fit. Support strategic partners, national laboratories, government organizations, and industry events while bringing customer feedback into product strategy.

Own end-to-end hardware system architecture for graphics compute platforms, GPU servers, and PCIe graphics form factors. Define physical topologies, high-speed interconnects, PCB stack-ups, power delivery, telemetry, and management infrastructure. Lead JDM/ODM engineering partners through layout, bring-up, validation, debug, failure analysis, DFX reviews, and high-volume manufacturing. Collaborate across silicon, signal and power integrity, thermal, and mechanical engineering teams to deliver high-performance graphics hardware.

The RTL Design / Microarchitecture Engineer will define and implement microarchitectural components, optimize performance, and collaborate with cross-functional teams.

As a Principal Design Verification Engineer, you will lead verification strategies and teams for complex IPs or full-chip SoCs, ensuring high-quality silicon delivery through comprehensive verification methodologies and cross-functional collaboration.

Responsible for full-chip or block-level physical design from netlist to GDSII, ensuring timing, power, and area targets are met. Collaborates with teams for design convergence and performs DRC/LVS/EM/IR debugging.

The Site Reliability Engineer will design, implement, and manage reliable infrastructure and services, ensuring operational excellence and uptime.

The Senior Design Verification Engineer develops and verifies silicon IP, optimizing and characterizing performance using advanced tools, while leading a team.

Lead end-to-end ASIC physical implementation from netlist to GDSII, covering synthesis support, floorplanning, placement, CTS, routing, signoff, timing closure across corners, ECO flows, physical verification (DRC/LVS/EM/IR), integrating hard macros, and automating PD flows with TCL/Python while collaborating with RTL, verification, and foundry teams to meet PPA targets.

Design and implement RTL and microarchitectural components for high-performance SoC/IP. Develop SystemVerilog/Verilog modules, optimize PPA, collaborate with verification and physical design teams, support IP integration and silicon bring-up, and contribute to documentation and methodology improvements.

Lead development, optimization, and verification of digital silicon IP. Create and maintain specifications and documentation. Characterize IP performance using FPGA simulation and emulation and collaborate with architecture, PD, and software teams from design through bring-up.

Lead SoC architecture definition for next-generation compute platforms. Drive tradeoffs across performance, power, area, bandwidth and latency; define memory hierarchy, NoC/interconnect, coherency, and subsystem partitioning. Lead performance modeling and workload analysis (C/C++/SystemC), integrate third-party IPs, collaborate with RTL, verification, physical design, firmware and software teams, support silicon bring-up, debugging, validation and roadmap planning.

Lead architecture definition and technical direction for next-generation GPUs. Define data-parallel microarchitecture and memory/coherency hierarchies, drive tradeoffs (performance/power/area), perform workload profiling and performance modeling, collaborate across RTL/verification/physical/firmware/software teams, support silicon bring-up and post-silicon tuning, and contribute to long-term roadmap planning.