Jobs at Bolt Graphics

Lead design and implementation of a high-performance host-side driver stack mapping industry-standard graphics and compute APIs (Vulkan, OpenGL, OpenCL, SYCL) onto a proprietary RISC-V GPU API. Contribute to open-source (Mesa), run Khronos conformance tests, participate in standards groups, coordinate with GPU driver team, and build tooling for development, optimization, and debugging.

Lead definition of data-parallel GPU microarchitecture, drive tradeoffs for performance/power/area, define memory hierarchy and coherency, perform performance modeling and workload analysis (C/C++/SystemC), collaborate across RTL, verification, physical design, firmware/software and systems teams, support silicon bring-up, debug and post-silicon optimization, and contribute to long-term product roadmap.

The CPU Compiler Lead will optimize code for a high-performance RISC-V CPU, manage integration of language standards, and lead compiler optimization efforts.

Lead the development of a high-performance compiler stack for GPU architecture, focusing on optimization passes, collaboration with hardware architects, and team coordination.

The RTL Design / Microarchitecture Engineer will define and implement microarchitectural components, optimize performance, and collaborate with cross-functional teams.

As a Principal Design Verification Engineer, you will lead verification strategies and teams for complex IPs or full-chip SoCs, ensuring high-quality silicon delivery through comprehensive verification methodologies and cross-functional collaboration.

Responsible for full-chip or block-level physical design from netlist to GDSII, ensuring timing, power, and area targets are met. Collaborates with teams for design convergence and performs DRC/LVS/EM/IR debugging.

Coordinate customer and partner onboarding, manage executive support and calendars, track sales pipeline and KPIs, maintain BD documentation, coordinate cross-functional projects, organize travel, support recruiting, and build scalable onboarding and enablement processes to grow business development operations.

Lead end-to-end hardware architecture for next-generation GPU compute platforms, define high-speed PCB topologies and PDNs, optimize PCIe/serdes fabrics, coordinate SI/PI and thermal co-design, and lead technical engagement with JDM/ODM partners through bring-up, failure analysis, and HVM transition.

The Site Reliability Engineer will design, implement, and manage reliable infrastructure and services, ensuring operational excellence and uptime.

Coordinate social media content and engagement, manage posting schedules, analyze performance, and support influencer marketing initiatives at Bolt Graphics.

The Senior Design Verification Engineer develops and verifies silicon IP, optimizing and characterizing performance using advanced tools, while leading a team.

Lead enterprise master data architecture and PLM implementation, design item master and lifecycle schemas, build data quality and ETL pipelines, integrate CAD/EDA and PLM with ERP/MES, oversee data governance, BOM audits, and supply-chain data syndication for high-volume semiconductor manufacturing.

The IT Business Systems Administrator manages core platforms like Jira and SharePoint, oversees ERP systems, and supports CRM tools, focusing on improving workflows and documentation for various operational teams.

Support cross-functional teams by owning operational workflows, vendor and office logistics, and ad hoc tasks. Coordinate IT, HR, Legal, Finance, Business Development, and Engineering workstreams, track progress, remove blockers, build consensus, and identify process improvements to increase organizational efficiency in a fast-paced startup environment.

Plan and oversee low-level software and driver development for graphics processors. Manage schedules, risks, deliverables, and cross-team coordination; report progress to stakeholders; improve PM processes; coordinate with other PMs; communicate closely with engineers and executives. On-site 3-4 days/week in the Bay Area with occasional travel.

Plan and oversee SoC/IC chip design programs, manage schedules and risks, coordinate global teams and other PMs, report progress to stakeholders, and improve PM processes to meet product goals.

The DevOps Engineer will migrate from GitHub to GitLab, manage CI/CD infrastructures, integrate cloud services, and ensure efficient delivery processes.

The role involves leading architecture definition for next-gen GPUs, driving performance modeling, integration, and collaboration across multiple teams. Responsibilities include defining microarchitecture, optimizing performance, and supporting silicon bring-up while contributing to product roadmap planning.

Design and implement RTL and microarchitectural components for SoC/IP using SystemVerilog/Verilog. Optimize PPA, collaborate with verification and physical design teams, support integration, timing closure, simulation, GLS, and silicon bring-up, and contribute to design documentation and reviews.