Jobs at Bolt Graphics

The RTL Design / Microarchitecture Engineer will define and implement microarchitectural components, optimize performance, and collaborate with cross-functional teams.

As a Principal Design Verification Engineer, you will lead verification strategies and teams for complex IPs or full-chip SoCs, ensuring high-quality silicon delivery through comprehensive verification methodologies and cross-functional collaboration.

Responsible for full-chip or block-level physical design from netlist to GDSII, ensuring timing, power, and area targets are met. Collaborates with teams for design convergence and performs DRC/LVS/EM/IR debugging.

Coordinate customer and partner onboarding, manage executive support and calendars, track sales pipeline and KPIs, maintain BD documentation, coordinate cross-functional projects, organize travel, support recruiting, and build scalable onboarding and enablement processes to grow business development operations.

The Site Reliability Engineer will design, implement, and manage reliable infrastructure and services, ensuring operational excellence and uptime.

The Senior Design Verification Engineer develops and verifies silicon IP, optimizing and characterizing performance using advanced tools, while leading a team.

Design and implement RTL and microarchitectural components for high-performance SoC/IP. Develop SystemVerilog/Verilog modules, optimize PPA, collaborate with verification and physical design teams, support IP integration and silicon bring-up, and contribute to documentation and methodology improvements.

Lead SoC architecture definition for next-generation compute platforms. Drive tradeoffs across performance, power, area, bandwidth and latency; define memory hierarchy, NoC/interconnect, coherency, and subsystem partitioning. Lead performance modeling and workload analysis (C/C++/SystemC), integrate third-party IPs, collaborate with RTL, verification, physical design, firmware and software teams, support silicon bring-up, debugging, validation and roadmap planning.

Lead development, optimization, and verification of digital silicon IP. Create and maintain specifications and documentation. Characterize IP performance using FPGA simulation and emulation and collaborate with architecture, PD, and software teams from design through bring-up.

Lead end-to-end ASIC physical implementation from netlist to GDSII, covering synthesis support, floorplanning, placement, CTS, routing, signoff, timing closure across corners, ECO flows, physical verification (DRC/LVS/EM/IR), integrating hard macros, and automating PD flows with TCL/Python while collaborating with RTL, verification, and foundry teams to meet PPA targets.

Lead architecture definition and technical direction for next-generation GPUs. Define data-parallel microarchitecture and memory/coherency hierarchies, drive tradeoffs (performance/power/area), perform workload profiling and performance modeling, collaborate across RTL/verification/physical/firmware/software teams, support silicon bring-up and post-silicon tuning, and contribute to long-term roadmap planning.

Lead enterprise master data architecture and PLM implementation, design item master and lifecycle schemas, build data quality and ETL pipelines, integrate CAD/EDA and PLM with ERP/MES, oversee data governance, BOM audits, and supply-chain data syndication for high-volume semiconductor manufacturing.

Plan and oversee low-level software and driver development for graphics processors. Manage schedules, risks, deliverables, and cross-team coordination; report progress to stakeholders; improve PM processes; coordinate with other PMs; communicate closely with engineers and executives. On-site 3-4 days/week in the Bay Area with occasional travel.

Support cross-functional teams by owning operational workflows, vendor and office logistics, and ad hoc tasks. Coordinate IT, HR, Legal, Finance, Business Development, and Engineering workstreams, track progress, remove blockers, build consensus, and identify process improvements to increase organizational efficiency in a fast-paced startup environment.

Plan and oversee SoC/IC chip design programs, manage schedules and risks, coordinate global teams and other PMs, report progress to stakeholders, and improve PM processes to meet product goals.

The DevOps Engineer will migrate from GitHub to GitLab, manage CI/CD infrastructures, integrate cloud services, and ensure efficient delivery processes.

Manage and maintain software configuration processes, repositories, baselines, and audits. Lead configuration control boards, produce compliance reports, train staff, resolve configuration discrepancies, and support cross-team product delivery to ensure software stability and integrity.

The role involves leading architecture definition for next-gen GPUs, driving performance modeling, integration, and collaboration across multiple teams. Responsibilities include defining microarchitecture, optimizing performance, and supporting silicon bring-up while contributing to product roadmap planning.

Lead Philippines finance and operations: manage GL/AP/AR, month/quarter/year-end close, inventory/COGS and equipment depreciation, prepare PFRS/IFRS financial statements, ensure BIR/SEC tax compliance and filings, handle audits, design SOPs and internal controls, leverage NetSuite/cloud ERP to automate reporting and support cross-functional budgeting and inventory tracking for a distributed team.

Conduct research on high-performance computing algorithms, translate advanced mathematics into discrete computational models, benchmark and analyze competing approaches, provide performance estimations, and collaborate with hardware architects to define proof-of-concept features and system requirements.