Teams at Bolt Graphics

The Senior Design Verification Engineer develops and verifies silicon IP, optimizing and characterizing performance using advanced tools, while leading a team.

Lead end-to-end ASIC physical implementation from netlist to GDSII, covering synthesis support, floorplanning, placement, CTS, routing, signoff, timing closure across corners, ECO flows, physical verification (DRC/LVS/EM/IR), integrating hard macros, and automating PD flows with TCL/Python while collaborating with RTL, verification, and foundry teams to meet PPA targets.

Design and implement RTL and microarchitectural components for high-performance SoC/IP. Develop SystemVerilog/Verilog modules, optimize PPA, collaborate with verification and physical design teams, support IP integration and silicon bring-up, and contribute to documentation and methodology improvements.