Top Engineering Jobs

The VP of Information Technology will lead and transform IT and cybersecurity, overseeing infrastructure, digital strategy, vendor management, and team leadership to support global operations in a growth-stage semiconductor technology company.

The Staff Engineer - DFT will implement DFT strategies for low-power SoCs, develop test architectures, and collaborate with teams for test vector integration and analysis.

The Senior Embedded Software Engineer will develop, integrate, and verify SDKs for SoC platforms, lead HAL and driver development, and validate embedded systems through collaboration across teams.

The Director of MCU Software will lead the execution and delivery of Ambiq's AmbiqSuite SDK for ARM Cortex-M MCUs, managing the software development lifecycle and ensuring high-quality releases.

The Field Application Engineer will support global customers in design-in activities, develop product solutions, optimize power consumption, and assist with customer HW/SW development.

The Field Application Engineer supports global customers by aiding in the design-in process of Ambiq's low-power semiconductor solutions, optimizing energy efficiency, and developing hardware and software for embedded systems. Responsibilities include design reviews, customer collaboration, debugging, and presenting complex technical topics.

Design and implement low-power DFT architecture for ultra-low-power SoCs: scan insertion, boundary scan, MBIST and ATPG; generate and optimize structural test vectors; run pre/post-layout simulations; collaborate with designers and test engineers to resolve timing, power, and logical issues and bring up tests on silicon.

Define, design, and implement system-level tests and automation for ARM Cortex-M, DSP, and NPU platforms. Develop firmware test frameworks in C/assembly and automation in Python, perform pre- and post-silicon validation on FPGA/emulation and silicon, debug across software and hardware layers, measure performance, and mentor junior engineers.

Lead and scale the physical implementation organization for ultra-low-power MCU products. Define strategy, build and mentor teams, oversee full-chip and block-level physical design (floorplanning, power planning, CTS, P&R, timing closure, DRC/LVS, EM/IR signoff), collaborate cross-functionally, manage schedules and tape-out readiness, and ensure first-silicon success and manufacturability.

Lead timing methodology and closure for block and SoC levels in modern FinFET/multi-patterning processes. Define flows, constraints, signoff correlation, timing margining, glitch noise analysis, and collaborate with RTL, PnR, DFT, and post-silicon teams to achieve timing convergence and best-in-class PPA.