Top Engineering Jobs

Lead development, layout, and optimization of high-speed datapath IO circuits for next‑gen NAND flash, driving AI-first workflows. Own architecture decisions, verify major IO blocks, redesign engineering workflows to embed AI, mentor teams, and collaborate across functions to meet aggressive data-rate and power targets.

Lead chemical and specialty gas construction engineering across design, construction, commissioning, and handover for large-scale semiconductor fab projects. Validate designs, resolve construction and installation issues, manage cost/schedule/risk, coordinate contractors/consultants, support root-cause analyses and BKMs, and apply AI tools to improve engineering analysis and project execution.

Lead development, validation, and qualification of next-generation HBM products. Optimize test coverage, improve yields and reduce test time, perform circuit analysis and Verilog-based design verification, recommend process conversions, resolve qualification/RMA issues, mentor team members, and drive cross-functional collaboration to deliver high-volume manufacturing targets.

Manage Facilities project execution, CAPEX optimization, and tool installation, ensuring alignment with engineering, operations, and business priorities.

Design and optimize NAND flash array circuits and waveforms; perform schematic, block-level, subsystem and full-chip simulations; lead layout implementation and parasitic extraction; collaborate with firmware, analog, validation, and manufacturing teams; develop Python automation and AI-assisted EDA utilities; evaluate die size, power, and reliability tradeoffs and produce documentation.

As a Principal Design Engineer, you'll architect high-performance DRAM circuits, collaborate with teams, perform advanced circuit simulations, and manage layout resources to optimize memory technologies.

Design and simulate mixed-signal and PHY-adjacent circuit blocks for HBM, develop behavioral models (Verilog-A/AMS or SystemVerilog), run SPICE and mixed-signal simulations, support parasitic modeling and validation, collaborate on integration and silicon bring-up.

Implement SoC physical design from netlist to GDSII: floor-planning, placement, CTS, routing, and optimization to meet PPA. Drive MMMC timing closure, integrate complex IP, perform physical signoff (DRC/LVS/IR/EM/timing), support tape-out and post-silicon debug, collaborate across RTL/DFT/packaging/manufacturing, and improve flows via scripting and AI-enabled tools.

Develop and test SSD firmware subsystems to meet performance, endurance, capacity, functionality, and reliability specs. Create firmware unit and functional tests, debug and modify embedded code (C, assembly, machine language, Python), integrate AI-assisted tools, communicate status to stakeholders, and mentor team members.

Develop and execute reliability test flows and qualification plans for HBM products; drive DPM reduction, root-cause failure analysis (EFA/PFA), process conversions, risk management, cross-functional collaboration, mentorship, and AI-enabled reliability improvements.