Principal Design Engineer

Posted 55 Minutes Ago
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San Jose, CA, USA
In-Office
176K-298K Annually
Senior level
Artificial Intelligence • Hardware • Information Technology • Machine Learning
Your talent powers our future.
The Role
Lead development, layout, and optimization of high-speed datapath IO circuits for next‑gen NAND flash, driving AI-first workflows. Own architecture decisions, verify major IO blocks, redesign engineering workflows to embed AI, mentor teams, and collaborate across functions to meet aggressive data-rate and power targets.
Summary Generated by Built In
Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a Principal Design Engineer in NVEG, you will lead the development, layout, and optimization of innovative datapath circuits for next-generation NAND flash memory, with AI utilization as a central pillar of how you work! You are expected to apply AI tools every day to accelerate design exploration, layout iteration, verification, and multi-functional communication, and - equally important - to redesign existing engineering workflows so that AI can be inserted where it delivers the highest leverage! You will act as a key technical leader, driving task forces, making architectural decisions to hit aggressive data-rate and power targets, and setting the standard for how an AI-augmented design engineer operates. Beyond individual productivity, you will mentor the team on how to think, plan, and implement in an AI-first environment.
What's Encouraged Daily:
  • AI Driven Daily Execution: Use AI tools (LLM-based assistants, code and RTL generation, spec parsing, waveform interpretation, layout suggestion engines) as a default part of daily engineering work. Continuously identify tasks where AI can replace, accelerate, or augment manual effort, and embrace new tools rapidly as they emerge.
  • Workflow Redesign for AI: Rearchitect existing design, verification, and debug workflows so that AI is a first-class participant, not a bolt-on. This includes restructuring specification documents, simulation setups, review checklists, and hand-off artifacts to be AI-consumable; building prompt libraries, agents, and scripts that automate recurring engineering patterns; and defining new review and sign-off flows that leverage AI-generated analysis.
  • AI Capability Leadership: Serve as a technical champion for AI adoption within the design team. Evaluate emerging AI tools and frontier models, run pilots, publish internal standard methodologies, and drive team-wide adoption of workflows that measurably reduce cycle time or improve design quality.
  • Technical Ownership: Manage, design, and verify major IO/datapath blocks (input receiver, serializer, deserializer, clock distribution, equalizer, ZQ calibration, ONFI training features, wave pipelines) to rigorously meet performance specifications - employing AI-assisted exploration, sizing, and verification wherever it accelerates convergence.
  • Multi-functional Integration: Collaborate closely with project integration and other functional design teams to define and negotiate block interface specifications. Use AI to summarize discussions, reconcile specs across teams, and surface inconsistencies early.
  • Customer & Systems Alignment: Liaise with Applications Engineering (Apps) to evaluate new specifications, balancing customer needs against design and physical constraints. Use AI to accelerate feasibility studies and quantify trade-offs.
  • Mentorship & Review: Document AI-augmented methodologies, present final results to expert panels and team members, and mentor new engineers on how to think and work in an AI-first environment - not just which tools to click.

Minimum Qualifications:
  • Bachelors or Masters degree in Electrical Engineering or a related field with 8+ years of relevant IC design experience.
  • Demonstrated, hands-on use of AI tools (LLM-based assistants, coding copilots, agentic workflows, or ML-based EDA aids) as a routine part of daily engineering work. Candidates must be able to describe concrete examples where AI meaningfully changed their productivity or design outcome.
  • Proven track record to redesign or create engineering workflows around AI capabilities - for example, restructuring specs, review flows, or verification pipelines so that AI can operate on them effectively; building custom prompts, scripts, or agents that automate recurring engineering tasks.
  • Good knowledge and deep intuitive understanding of high-speed IO circuit performance, power/area optimization, and top-level chip architecture/floorplanning.
  • Proven track record in physical design flows, layout optimization, and parasitic extraction.
  • Growth mindset toward AI - willingness to continuously learn new tools, retire old habits, and rethink established workflows as AI capability evolves.

Preferred Qualifications:
  • Experience building or deploying custom AI agents, LLM pipelines, or ML models targeted at IC design, verification, layout, or silicon debug problems.
  • Familiarity with prompt engineering, retrieval-augmented generation (RAG), fine-tuning, or agentic frameworks applied to engineering workflows.
  • Experience quantifying the productivity or quality impact of AI driven workflow changes (cycle-time reduction, defect escape reduction, coverage improvement, etc.).
  • Experience with DRAM interfaces (e.g., DDR4/5, LPDDR5/6, HBM3/3E/4) or other high-speed industry-standard interfaces.
  • Comprehensive understanding of sophisticated CMOS device physics, device reliability mechanisms, BSIM modeling, and CMOS targets for high-speed IO operation.

The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$176,000.00 - $298,000.00 a year
Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits .
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn about your right to work click here.
To learn more about Micron, please visit micron.com/careers
US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron's People Organization at [email protected] or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Skills Required

  • Bachelor's or Master's in Electrical Engineering or related field with 8+ years of relevant IC design experience
  • Demonstrated hands-on use of AI tools (LLM-based assistants, coding copilots, agentic workflows, or ML-based EDA aids) as routine part of daily engineering work
  • Proven track record to redesign or create engineering workflows around AI capabilities (restructuring specs, review flows, verification pipelines; building prompts, scripts, or agents)
  • Deep knowledge of high-speed IO circuit performance, power/area optimization, and top-level chip architecture/floorplanning
  • Proven experience in physical design flows, layout optimization, and parasitic extraction
  • Growth mindset toward AI and willingness to continuously learn and adapt workflows
  • Experience building or deploying custom AI agents, LLM pipelines, or ML models for IC design, verification, layout, or silicon debug
  • Familiarity with prompt engineering, RAG, fine-tuning, or agentic frameworks applied to engineering workflows
  • Experience quantifying productivity or quality impact of AI-driven workflow changes (cycle-time reduction, defect escape reduction, coverage improvement)
  • Experience with DRAM interfaces (DDR4/DDR5, LPDDR5/LPDDR6, HBM3/3E/4)
  • Comprehensive understanding of CMOS device physics, device reliability, BSIM modeling, and CMOS targets for high-speed IO

Micron Technology Compensation & Benefits Highlights

  • Retirement Support The RAM 401(k) plan provides a dollar‑for‑dollar company match up to 5% of eligible pay with automatic enrollment and escalation. After‑tax contributions and in‑plan Roth conversions add flexibility for additional savings.
  • Healthcare Strength Multiple medical plan options with HSA/FSA support, mental‑health resources, and wellness programs are documented. Access to the Micron Family Health Center at Boise for enrollees adds onsite care in certain locations.
  • Equity Value & Accessibility An Employee Stock Purchase Plan enables purchases of company stock at a 15% discount in multiple regions. Company materials also reference equity participation, reinforcing employee ownership opportunities.

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The Company
HQ: Boise, ID
45,000 Employees
Year Founded: 1978

What We Do

We are a world leader in innovative memory solutions that transform how the world uses information to enrich life for all. For over 45 years, our company has been instrumental to the world’s most significant technology advancements, delivering optimal memory and storage systems for a broad range of applications.

Why Work With Us

Global opportunities, team member development, and career advancement—Micron invests in you and celebrates your skills, a growth mindset, and the tenacity to strive. At Micron, everyone innovates.

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Employees engage in a combination of remote and on-site work.

Micron recognizes the importance of maintaining a healthy work-life balance to foster a culture of collaboration, innovation and meet the needs of the business. In alignment with these values, we offer four flexible work arrangement options

Typical time on-site: Flexible
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