Senior/Staff ASIC Engineer

Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Position Overview
We are seeking a motivated Staff SoC Design Integration Engineer to join our SoC design team in Taipei or Hsinchu. This role sits at the heart of SoC integration, working across multiple disciplines to bring complex chip designs from RTL to silicon. A major focus of this role is the adaptation and integration of AI-driven methodologies into SoC design workflows - leveraging large language models, machine learning, and intelligent automation to accelerate integration tasks, improve design quality, and push the boundaries of what's possible in modern chip design. The ideal candidate has solid hands-on experience in at least one area of SoC integration methodology, a strong desire to grow across the full spectrum of integration disciplines, and genuine curiosity about applying AI to transform traditional EDA workflows. Depending on the candidate's strengths and interests, this role offers the opportunity to expand into all facets of SoC design integration - from front-end quality checks to back-end signoff and silicon validation.
Key Responsibilities

• Participate in full-chip SoC integration activities spanning front-end and back-end design flows.
• Drive the adoption of AI and machine learning techniques to automate, optimize, and enhance SoC integration workflows, including but not limited to:
  • AI-assisted RTL analysis, constraint generation, and design rule checking
  • LLM-driven scripting, debugging, and root-cause analysis
  • Intelligent triage and prioritization of design violations
  • Building and curating datasets from design iterations to enable continuous AI-driven improvement
• Contribute to one or more of the following SoC integration disciplines, with opportunities to grow across all areas:
  • Lint & RTL Quality Checks - Run and debug lint (Spyglass/Ascent) to ensure RTL coding quality and design rule compliance.
  • Clock Domain Crossing (CDC) - Analyze and resolve CDC issues; review synchronizer structures and verify crossing schemes.
  • Design-for-Test (DFT) - Support scan insertion, ATPG, MBIST integration, and test coverage closure.
  • Timing Constraints & STA - Develop and validate SDC constraints; support timing closure across synthesis, P&R, and signoff.
  • Gate-Level Simulation (GLS) - Set up and debug gate-level simulations with SDF back-annotation to catch functional and timing issues post-synthesis/P&R.
  • Power Estimation & Analysis - Perform power analysis using activity-based and vectorless methods; identify and help mitigate power hotspots.
  • UPF / Multi-Voltage Design - Define or verify power intent (UPF); ensure correct isolation, level-shifting, and retention strategies.
  • Formal Verification & ECO - Run equivalence checking (LEC); support functional ECOs and netlist modifications through tapeout.
• Collaborate with RTL designers, physical design, DFT, analog/IP teams, and verification engineers to resolve integration issues.
• Develop and improve automation scripts (Tcl, Python, Perl) to enhance flow efficiency and repeatability.
• Evaluate and prototype emerging AI/ML tools and agentic workflows for EDA applications; share findings and best practices with the broader team.
• Support silicon bring-up debug when integration-related issues arise.

Required Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science with 8+ years of relevant experience; or Master's degree with 6+ years; or PhD with 2+ years.
• Solid working experience in at least one of the following areas: lint, CDC, DFT, timing constraints/STA, gate-level simulation, power estimation, UPF, or formal verification/ECO.
• Strong interest in applying AI and automation to chip design workflows - willingness to experiment with LLMs, ML models, and AI-assisted EDA tools is essential.
• Familiarity with industry-standard EDA tools (e.g., Spyglass, Conformal, Tessent, PrimeTime/Tempus, VCS/Xcelium, Joules/PowerArtist, or equivalent).
• Proficiency in at least one scripting language (Tcl, Python, or Perl).
• Strong problem-solving skills and the ability to work across multiple engineering teams.
• Good communication skills in English and Mandarin.

Preferred Qualifications

• Experience with large, multi-million-gate SoC designs.
• Exposure to more than one of the integration disciplines listed above.
• Hands-on experience with AI/ML tools for EDA - such as LLM-based code generation, AI-assisted debugging, or ML-driven optimization in design flows.
• Understanding of SoC physical design flows (synthesis, P&R, CTS, signoff).
• Experience with AMBA bus protocols (AXI/AHB) or SoC interconnect integration.
• Familiarity with memory controller or storage SoC architectures.
• Curiosity and willingness to learn new disciplines - this role is designed for growth.

About Micron Technology, Inc.
We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities - from the data center to the intelligent edge and across the client and mobile user experience.
To learn more, please visit micron.com/careers
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