Staff Package Design Engineer

Posted 14 Hours Ago
Be an Early Applicant
Tempe, AZ, USA
Hybrid
Senior level
3D Printing
The Role
Lead architecture and physical design for advanced semiconductor packages, including 2.5D/3D chiplets, interposers, bridges, RDL, and FCBGA solutions. Define package design rules and assembly methods, coordinate with silicon, SI/PI, thermal, manufacturing, foundry, substrate, and OSAT teams, manage package layout and manufacturing releases, and mentor package design engineers.
Summary Generated by Built In
Job Description

In this role, you will work at the intersection of IC design, advanced package development, and system-level implementation. As a Staff-level contributor, you will serve as the technical focal point, guiding the architecture and physical design of next-generation, high-performance semiconductor packages, including 2.5D/3D heterogeneous integration, chiplet-based architectures, high-density interposers, and advanced substrate technologies.

This role requires deep expertise in advanced packaging R&D, cross-domain co-design, and the ability to define methods and procedures for complex, multi-die integration assignments. You will lead cross-functional alignment with global silicon design, signal integrity/power integrity (SI/PI), thermal, and product engineering teams, while driving the creation of new packaging design rules and methodologies.

Key Responsibilities

  • Physical Architecture Leadership: Lead package layout architecture and physical design for next-generation heterogeneous integration, including 2.5D/3D chiplet packaging, high-density interposers, bridge technologies (e.g., EMIB equivalents), RDL, and advanced FCBGA solutions.
  • Methodology & Design Rules: Define, establish, and optimize package design rules and assembly Best Known Methods (BKMs); partner with foundries, substrate vendors, and OSATs to evaluate and validate advanced packaging capabilities, DRCs, and manufacturing limits.
  • Cross-Functional Technical Focal Point: Act as the primary package architecture lead across SI/PI, thermal, tooling, and platform integration teams. Lead design reviews to establish project scope, align stakeholder requirements, and balance pin budgets against electrical and mechanical trade-offs.
  • Layout & Release Management: Manage the complex package design cycle—including footprint assignment, stack-up structures, high-speed escape routing, power/ground distribution, and generation of manufacturing release outputs (Gerber/drill data, bump maps, assembly drawings).
  • Mentorship: Provide technical mentorship and guidance to junior and intermediate package design engineers, establishing standardized CAD workflows, layout techniques, and technical training to drive consistent execution across the department.

Qualifications

Experience

  • 8+ years of related experience with a Bachelor’s degree (or 6+ years with a Master’s degree); OR 5+ years of intensive R&D experience in advanced 2.5D/3D heterogeneous packaging (bridge/interposer architectures) with demonstrated experience establishing new design rules and authoring engineering BKMs.
  • Advanced Packaging Expertise: Strong background in advanced substrate-based packages, flip-chip layout, multi-die/chiplet-based architectures, thermal mitigation, and high-density routing.
  • CAD Proficiency: High proficiency with industry-standard package design tools, specifically Siemens/Mentor Xpedition (Layout / Substrate Integrator), Valor NPI, and/or Cadence Allegro Package Designer / SiP Layout.
  • Cross-Disciplinary Acumen: Working understanding of SI/PI fundamentals, impedance control, crosstalk mitigation, and the ability to balance these constraints against pin budgets and platform integration requirements.
  • Leadership & Communication: Strong communication and technical documentation skills, with a proven ability to lead multi-disciplinary test vehicle or product design meetings and secure tooling/supplier approvals independently.

Education

  • Bachelor's or Master's degree in Mechanical Engineering, Electrical Engineering, Microelectronics, Materials Science, or a related technical discipline.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.

Skills Required

  • 8+ years of related experience with a bachelor's degree, or 6+ years with a master's degree, or 5+ years of intensive advanced 2.5D/3D packaging R&D experience
  • Advanced experience with substrate-based packages, flip-chip layout, multi-die or chiplet architectures, thermal mitigation, and high-density routing
  • Proficiency with Siemens/Mentor Xpedition, Substrate Integrator, Valor NPI, and/or Cadence Allegro Package Designer or SiP Layout
  • Working knowledge of signal integrity, power integrity, impedance control, and crosstalk mitigation
  • Experience establishing package design rules and authoring engineering best-known methods
  • Ability to lead multidisciplinary design meetings and secure tooling and supplier approvals independently
  • Strong communication and technical documentation skills
  • Bachelor's or master's degree in Mechanical Engineering, Electrical Engineering, Microelectronics, Materials Science, or a related technical discipline

Renesas Electronics Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Renesas Electronics and has not been reviewed or approved by Renesas Electronics.

  • Fair & Transparent Compensation — Feedback suggests pay is generally fair-to-good across many roles, with base pay aligned to prevailing market levels in multiple U.S. locations. Engineering and leadership tracks can be competitive on total compensation, reinforcing a sense that pay can meet market expectations in key job families.
  • Healthcare Strength — Feedback suggests core medical, dental, and vision coverage is solid and well-regarded by employees. Day-one eligibility in U.S. roles is described, supporting confidence in access and continuity of care.
  • Leave & Time Off Breadth — Feedback suggests PTO, paid holidays, sick time, and parental leave provide a comprehensive time-off framework. Company initiatives like Renesas Day and meeting-light Focus Fridays further support time away and balance.

Renesas Electronics Insights

Am I A Good Fit?
beta
Get Personalized Job Insights.
Our AI-powered fit analysis compares your resume with a job listing so you know if your skills & experience align.

The Company
HQ: Tokyo
10,040 Employees

What We Do

We're the world's leading semiconductor manufacturer. Our mission is to make our lives easier and a world that's safer, healthier, greener, and smarter.

Similar Jobs

CDW Logo CDW

Support Engineer

Information Technology
Remote or Hybrid
US
15100 Employees
78K-108K Annually

CDW Logo CDW

Software Engineer

Information Technology
Remote or Hybrid
US
15100 Employees
86K-119K Annually

Hilton Logo Hilton

Receptionist

Events • Food • Travel • Hospitality • Hotels & Resorts
In-Office
Sedona, AZ, USA
500000 Employees

The Aerospace Corporation Logo The Aerospace Corporation

Honeywell Aerospace Early Career – IT Analyst

Aerospace • Artificial Intelligence • Cloud • Machine Learning • Software • Cybersecurity • Defense
Remote or Hybrid
United States
4600 Employees
80K-109K Annually

Similar Companies Hiring

Vast Thumbnail
Software • Manufacturing • Hardware • Aerospace • 3D Printing
Long Beach, CA
655 Employees

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account