Jobs at Renesas Electronics

Architects, designs, verifies, and optimizes CMOS analog blocks and high-speed DDR5/DDR6 I/O interfaces for custom ASICs. Analyzes silicon ATE and bench data, performs simulations, ensures signal integrity and circuit reliability, and collaborates with digital, systems, verification, validation, and test teams. Provides technical leadership and mentorship, documents designs, and ensures layouts meet analog matching and performance standards while satisfying power, area, and timeline constraints.

Lead development and execution of IR strategy, perform market intelligence and competitor/shareholder analyses, provide actionable feedback to management, manage investor/analyst communications and materials, and coordinate disclosures with FP&A and Accounting to enhance corporate valuation.

Provide test operations and engineering support for post-release products across test manufacturing sites in Asia. Manage daily test operations, lot tracking, test program releases, hardware troubleshooting, tester utilization/OEE, capacity expansions, deployment of test technology, process improvements, and drive yield and margin improvements.

Own and grow a portfolio of enterprise accounts by developing strategic account plans, driving expansion and renewals, managing complex sales cycles, negotiating commercial agreements, coordinating cross-functional delivery, maintaining accurate CRM data in Salesforce, and ensuring high customer satisfaction through executive engagement and on-site visits.

Qualify and develop new software sales leads, execute KPI-driven campaigns, maintain Salesforce CRM notes, collaborate with sales and technical teams, and recommend Altium platforms to customers while learning product and industry trends.

Deploy and configure the Altium Agile Platform for mid-market customers, translate engineering workflows into system configurations, assist with PLM-lite practices, troubleshoot technical issues, document implementations, support data migrations, and collaborate with Professional Services, Sales, and Product teams to ensure adoption.

Lead product quality for new product introduction and volume ramp of PCP products for AI datacenters. Drive continuous improvement, analyze DPPM and customer returns, ensure customer-specific quality requirements and audit readiness, lead cross-functional problem solving, manage supplier excursions and escalations, and represent the business on external standards committees.

Lead regional marketing for automotive MCUs in China: develop positioning, go-to-market strategies, customer and partner relationships, ecosystem development, competitor and market analysis, and sales enablement to drive DIN and business growth.

Define and validate system-level solutions for input protection devices in enterprise, data center, telecom, and industrial power systems. Drive product definition, customer engagement, system architecture, validation strategies, reference designs, lab bring-up, failure analysis, documentation, and cross-functional NPI support from concept through production ramp.

Lead corporate FP&A activities including annual planning, forecasting, consolidated P&L and cash flow analysis, variance analysis, management reporting, scenario modeling, cross-functional partnership, and process automation to support executive decision-making and strategic initiatives.

Develop and maintain secure, high-performance backend services. Participate in sprint planning, estimate and complete tasks, write unit and high-level tests, integrate frontend logic, use GitLab/GitHub for source control, deploy/configure on AWS, and contribute to process improvements.

Provide hands-on applications support for input protection devices in high-current/high-voltage systems. Tasks include schematic and PCB reviews, board bring-up, debug, validation, creating evaluation and reference designs, lab characterization using test equipment, writing customer documentation, and collaborating with cross-functional teams to resolve customer issues and improve product robustness.

Lead and technically drive development of configurable mixed-signal ASICs: define architecture and IP requirements, create verification plans, coordinate cross-functional teams (test, qualification, QA), ensure best practices and documentation, and mentor a team of analog designers to product release.

Develop mixed-signal ATE test methodologies, create low-cost/high-yield test hardware and software, debug silicon, support production test release, reduce test time, assist yield and reliability efforts, and collaborate with design, DFT, product and quality teams.

Support validation of digital multiphase controllers and power stage modules by planning evaluations, writing Python scripts and hardware automation, performing lab measurements, debugging, analyzing data, reporting results, and correlating ATE to bench. Collaborate with design, firmware, GUI, and test engineering teams to ensure functional and parametric compliance with specifications.

Leads a global test engineering organization responsible for end-to-end test strategy, including DFT, characterization, qualification, wafer sort, final test, production release, and sustaining. Owns test cost, yield, quality, capacity planning, and manufacturing readiness for semiconductor power products. Partners cross-functionally to resolve test escapes, yield excursions, and customer returns while driving ATE standardization, automation, data systems, and AI-enabled engineering practices. Develops technical leaders and ensures predictable NPI execution and high-volume production success.

Graduate Engineer supporting digital IP and subsystem development for SoC and ASIC products. Responsibilities include RTL design using Verilog/SystemVerilog, microarchitecture support, simulation, lint and CDC checks, functional verification, debugging, documentation, and cross-functional collaboration. The role provides mentorship and exposure to the full semiconductor chip design lifecycle.

Lead architecture, design, simulation, verification and validation of CMOS analog blocks for custom ASICs (Rx, Tx, PLL, bandgap, high-speed mixed-signal). Optimize DDR I/O interfaces, ensure signal integrity, low-power operation, EM/IR/aging reliability, and high-quality layouts. Provide technical leadership, mentor junior engineers, collaborate with digital and systems teams, and produce thorough documentation and design verification.

Lead architecture, design, simulation, verification, and layout of high-performance CMOS analog blocks (Rx, Tx, PLL, bandgap) for custom ASICs. Optimize high-speed DDR I/O and receiver circuits (CTLE, VGA, DFE, slicer), ensure signal integrity, low-power operation, reliability (EM/IR/aging), mentor junior engineers, and produce design documentation.

Lead architecture, design, simulation, verification and layout of CMOS analog blocks (Rx, Tx, PLL, bandgap, high-speed mixed-signal) for custom ASICs. Mentor junior engineers, collaborate with digital/systems teams, ensure signal integrity, reliability (EM/IR/aging), and low-power performance, and produce thorough documentation and validation.