As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
Responsibilities - What you’ll do
- Own the complete physical design implementation for CPU blocks or sub-systems, including synthesis, place & route, and signoff.
- Optimize implementation for aggressive PPA goals, working across complex pipeline and control logic.
- Collaborate with RTL, microarchitecture, and power teams to drive co-design closure and resolve physical bottlenecks early in the design cycle.
- Analyze and debug timing, congestion, and physical design issues across the flow and implement fixes efficiently.
- Support and improve physical design flows, automation, and methodology across nodes and product generations.
- Work on designs targeting advanced and legacy nodes and adapt implementation strategies for tech challenges.
Requirements - What you’ll bring
- 8+ years of hands-on experience in physical design implementation.
- Strong technical analysis skills, detail-oriented mindset and clear communication.
- Proficient in EDA tools for synthesis and place & route (Synopsys or Cadence or similar industry tools and flows)
- Proficient in physical design concepts: synthesis, floorplanning, placement, CTS, routing, and signoff closure.
- Good scripting skills in TCL, Python, or Perl for flow automation.
- Exposure to CPU core implementation or high-performance digital designs is preferred.
Why join us?
- Be part of the RISC-V movement and work on world-class RISC-V CPU IP.
- Collaborate with world-class engineers in a supportive, fast-paced, learning environment.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
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What We Do
The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
