Jobs at SiFive

Design and implement CPU microarchitecture features and ISA extensions using Chisel; integrate into Chisel/FIRRTL framework; perform sandbox verification and collaborate with verification, physical implementation, and performance teams to meet frequency, area, power, and performance goals. Produce documentation and participate in collaborative design.

Analyze and benchmark SiFive IP power consumption, correlate power models with RTL and silicon, work with architects and designers to optimize power/performance trade-offs, and innovate improvements to power analysis flows.

Lead a performance engineering team to research, model, and develop high-performance core architectures and microarchitectures. Design experiments, identify HW/SW bottlenecks, and work with design teams to implement and deliver performance targets in RTL and FPGA flows.

Research, model, and develop microarchitecture features for high-performance RISC-V processors. Design and run experiments, identify HW/SW performance bottlenecks, perform workload characterization and reduction, and collaborate with design teams to implement and deliver performance targets in RTL and FPGA prototypes.

Lead a performance engineering team to research, model, and develop high-performance CPU core architectures. Design experiments, analyze HW/SW performance bottlenecks, and work with design teams to implement and deliver RTL targets.

Lead verification planning and execution for high-performance out-of-order CPU core blocks. Define verification strategy, develop robust UVM/SystemVerilog environments, write checkers/assertions, drive coverage closure, debug complex microarchitectural issues, and partner with architecture, RTL, performance, and software teams to raise verification quality and provide reusable methodology.

Lead verification planning and execution for high-performance out-of-order CPU core blocks. Define verification strategy, build testbenches, assertions, and coverage models, perform root-cause debug, work with architecture/RTL/performance teams, and drive verification closure and reusable methodology across core generations.

Lead functional verification for high-performance out-of-order CPU cores. Plan and execute block-to-core verification, develop UVM/SystemVerilog testbenches, write coverage and assertions, create constrained-random and directed tests, debug failures, collaborate with architects and RTL teams, and contribute reusable DV methodology and infrastructure to achieve signoff-quality verification.

Lead verification planning and execution for high-performance out-of-order CPU core blocks (frontend, midcore, LSU, prefetch). Define verification strategies, develop environments, assertions, scoreboards, stimulus and coverage models, perform root-cause debug, partner with architecture and design teams, and deliver reusable methodology to close microarchitectural risks and achieve signoff.

Drive functional verification for high-performance out-of-order CPU cores: create verification plans, develop UVM/SystemVerilog testbenches, write assertions and coverage, run constrained-random and directed tests, analyze/debug failures, and build reusable DV methodology and infrastructure to achieve verification signoff.

Lead verification of L2/L3 cache and memory-subsystem features focusing on coherency, ordering, and integration. Build and maintain UVM/SystemVerilog testbenches, assertions, checkers, scoreboards, coverage models; develop directed and constrained-random tests; analyze failures, root-cause across RTL and testbench; drive fixes and improve verification methodology, automation, and debug infrastructure.

Lead verification of cache and memory-subsystem functionality focused on coherency, ordering, correctness, and integration. Create verification strategies and test plans; develop testbenches, checkers, assertions, stimulus, and coverage; run directed and constrained-random tests; debug failures and drive fixes across RTL and infrastructure; collaborate with architecture and design teams; and improve methodology, automation, and team-wide verification quality.

Lead verification planning and execution for L2/L3 caches and cache-subsystem integration. Build and maintain SystemVerilog/UVM testbenches, checkers, assertions, scoreboards, constrained-random tests, and coverage models. Debug complex RTL/testbench issues, drive fixes, collaborate with architecture and design teams, close coverage holes, and contribute reusable methodology and automation to improve team verification quality and scalability.

Drive physical implementation and timing closure for high-performance chip designs. Architect advanced clock distribution and global interconnects, optimize RC/jitter/IR issues, collaborate with RTL/architecture teams, mentor engineers, and sign off on implementation using industry EDA tools.

Develop and maintain a scalable Verification Platform including VIPs, AIPs, and testbench components. Architect libraries in Scala/Chisel, build SystemVerilog/UVM VIPs, create test plans and testbenches, and educate DV teams on best practices.

The Senior Design Verification Engineer will ensure functional correctness of SoCs/IPs, focusing on verification plans, environment development, debugging, coverage closure, and mentoring junior engineers.

Lead end-to-end physical design (synthesis, floorplan, P&R, signoff) for complex IPs, co-optimize RTL and microarchitecture to meet aggressive PPA targets, solve timing/routing/IR issues, apply advanced techniques across product classes, and mentor junior engineers.

Develop and maintain a modular build flow for Synopsys ZeBu and FPGA platforms, perform root-cause failure analysis across RISC-V hardware and software, use ZeBu/ILA/JTAG debugging features, automate debug workflows with Python/Bash, and collaborate with software and validation teams to integrate ZeBu runtime into SiFives internal build ecosystem.

Design, develop, upstream and release system software (Linux kernel, device drivers, OpenSBI, U-Boot, Yocto). Collaborate with architecture and hardware teams to integrate hardware features, debug complex multicore systems, and support device interfaces like PCIe, Ethernet, and CXL.

Develop and maintain a scalable Verification Platform: extend Chisel/CIRCT, build Scala libraries and Python tools for test harnesses, stimulus, and metadata querying, support end-to-end verification flows, and educate DV teams on best practices.