Jobs at SiFive

Leads functional safety and reliability work for processor and SoC platforms across automotive, robotics, AI, and data center applications. Owns safety requirements, goals, traceability, risk analysis, verification, assessments, audits, certification, and customer support. Applies ISO 26262, FMEDA, fault modeling, diagnostic coverage, safety cases, and fault injection. Coordinates architecture, design, verification, software, quality, product, program management, and customer-facing teams while addressing RAS mechanisms and technical risks.

Develop and maintain CPU block and subsystem verification environments using SystemVerilog and UVM. Extract requirements, create directed and constrained-random tests, achieve coverage goals, debug simulation failures, collaborate with RTL designers, and optimize automated regressions. The role may involve RAS verification, including ECC, parity, data poisoning, fault injection, and RISC-V ISA validation.

Own formal verification strategies for advanced out-of-order CPU cores. Responsibilities include creating formal test plans, implementing Chisel-based verification environments, applying abstraction techniques, debugging RTL failures, automating verification scripts, maintaining assertion libraries, reviewing proofs, and training team members. Requires extensive digital hardware formal verification experience, familiarity with VC Formal or JasperGold, and knowledge of VHDL, Verilog, or SystemVerilog.

Own end-to-end verification of CPU core components and microarchitectural features, including out-of-order execution, branch prediction, cache coherency, virtual memory, RAS, and functional safety. Develop SystemVerilog/UVM testbenches, constrained-random tests, scoreboards, checkers, and coverage models. Drive regressions, debug simulation and emulation failures, validate ISA behavior, and achieve coverage closure in collaboration with architecture and design teams.

Develop and maintain a scalable Verification Platform including VIPs, AIPs, and testbench components. Architect libraries in Scala/Chisel, build SystemVerilog/UVM VIPs, create test plans and testbenches, and educate DV teams on best practices.

Lead design verification for complex out-of-order CPU cores and memory subsystems. Own verification strategies, SystemVerilog/UVM testbenches, constrained-random stimulus, assertions, coverage models, debug, and sign-off. Verify core pipelines, caches, TLBs, MMU interfaces, memory ordering, coherence, exceptions, interrupts, and recovery paths. Collaborate with RTL, microarchitecture, performance, and post-silicon teams while mentoring verification engineers and influencing methodology across projects.

Develop and maintain the Verification Platform, collaborate with engineers to create reusable testbench components, and educate teams on best practices.

Lead end-to-end design verification for complex CPU cores, including fetch, decode, execution, memory, pipelines, caches, and MMUs. Develop verification strategies, test plans, UVM testbenches, constrained-random tests, scoreboards, checkers, and functional/code coverage models. Validate out-of-order execution, branch prediction, cache coherency, virtual memory, paging, exceptions, interrupts, and ISA compliance. Drive regressions, debug simulation and emulation failures, and partner with architecture and design teams to achieve verification closure.

Own end-to-end physical design implementation from synthesis through signoff for advanced IPs. Partner with architecture and RTL teams to optimize power, performance, and area, resolve timing and congestion challenges, improve design flows and automation, and mentor junior engineers. The role covers major IP domains including CPUs, fabrics, caches, memories, and accelerators, using Synopsys or Cadence implementation and signoff tools.

Develop and maintain a Verification Platform for Design Verification. Collaborate with engineers to create reusable testbench components and educate teams on best practices.

Owns Workday configuration, enhancements, reporting, security, workflows, integrations, testing, releases, and optimization across Recruiting, Compensation, Performance, Benefits, and HCM. Partners with HR, IT, Finance, Payroll, vendors, and business leaders to translate requirements into scalable solutions, troubleshoot issues, maintain documentation, support global operations, and improve system performance, data quality, security, and user experience.

Architect, design, and implement high-performance coherent cache subsystems for RISC-V CPU cores. Develop microarchitecture specifications, perform initial verification, create test plans, collaborate on physical implementation and optimization, and work with performance modeling teams to meet frequency, area, power, and performance goals.

Lead RTL-to-GDS physical design methodology for high-performance CPU cores at advanced TSMC N3 and N2 nodes. Architect automated, ML-driven flows to optimize power, performance, and area; define hierarchical floorplanning and integration strategies; partner with EDA and IP providers; build scalable flow automation, dashboards, and execution systems; and guide early PPA modeling and timing, IR drop, electromigration, and crosstalk closure.

Provides senior technical support for complex semiconductor physical design issues from RTL synthesis through place-and-route and post-route signoff. Responsibilities include debugging EDA tool and implementation problems, optimizing power, performance, and area targets, developing reference flows and technical documentation, and communicating customer feedback to internal engineering and R&D teams.

Lead end-to-end physical implementation of high-speed NoC and Uncore subsystems from RTL to GDSII. Drive architecture and physical-design co-optimization, floorplanning, macro placement, timing closure, routability, clock and reset distribution, and PPA improvements on advanced FinFET nodes. Develop implementation methodologies and automation, solve interconnect challenges, and mentor engineers while partnering with RTL and architecture teams.

Provides customer-facing technical support for SiFive processor IP and datacenter platforms. Resolves software issues involving simulations, toolchains, firmware, operating systems, and hardware development platforms; performs benchmarking and performance analysis; delivers customer training and demonstrations; creates documentation and application notes; and collaborates with engineering, sales, and marketing as a technical escalation point.

Join SiFive to optimize and deploy AI models on RISC-V architectures, focusing on heterogeneous computing, inference stack integration, and kernel/compiler synergy.

Develop high-performance AI/ML software for RISC-V architectures, including compiler infrastructure, runtime systems, model sharding, distributed execution, and performance optimization. Build and optimize LLM and generative AI deployments using MLIR, IREE, Triton, and related frameworks. Collaborate with hardware architects on AI accelerator and microarchitecture co-design, while contributing to open-source compiler and AI/ML projects.

Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.

Lead functional verification for a cache-coherent interconnect subsystem in high-performance SoCs. Develop UVM environments, checkers, scoreboards, assertions, stimulus, and coverage models; verify coherency, ordering, flow control, buffering, QoS, protocols, and integration paths. Create directed and constrained-random tests, debug failures across RTL and verification layers, close coverage gaps, and collaborate with architecture, design, formal, and software teams to improve methodology and verification quality.