Jobs at SiFive

Own formal verification strategy and execution for complex out-of-order processor blocks. Identify suitable blocks, create formal test plans, develop Chisel-based verification environments, apply abstraction and proof techniques, debug RTL failures, automate verification scripts, maintain assertion libraries, and guide teams on formal verification tools and methodologies.

Analyzes and optimizes SiFive IP power consumption across architecture, logic, circuit, RTL, and silicon levels. The role develops power models, correlates them with RTL and silicon results, guides performance-power tradeoffs for high-performance out-of-order CPUs, and improves power analysis workflows. Candidates need advanced computer architecture education, 5+ years of power benchmarking and ASIC optimization experience, and strong problem-solving skills.

Own verification planning, execution, debugging, coverage closure, and methodology for high-performance out-of-order RISC-V CPU core components. Develop SystemVerilog and UVM environments, assertions, scoreboards, stimulus, and coverage models. Partner with architecture and RTL teams to identify risks, resolve microarchitectural issues, and achieve signoff quality across frontend, midcore, load-store, execution, vector, and hardware prefetch units. Mentor engineers and improve verification infrastructure and practices across future CPU generations.

Own functional verification for high-performance out-of-order RISC-V CPU core units from block level through core integration. Develop test plans, UVM environments, testbenches, checkers, scoreboards, assertions, constrained-random tests, and coverage models. Debug failures, identify RTL and verification issues, close coverage gaps, and collaborate with architecture, design, performance, and software teams. Contribute reusable verification infrastructure and methodology for future CPU generations.

Staff Design Verification Engineer responsible for planning and executing verification for high-performance out-of-order RISC-V CPU cores, including vector functionality and microarchitectural interactions. Develops verification environments, checkers, scoreboards, assertions, stimulus, and coverage models; leads debug and coverage closure; partners with architecture and design teams; improves verification methodology; and mentors engineers.

Own formal verification for high-performance out-of-order RISC-V CPU cores, including planning, assertions, proof strategies, abstraction, debugging, and signoff closure. Develop scalable formal environments and infrastructure for control, ordering, pipeline, load-store, clock-gating, and microarchitectural behavior. Analyze failures and coverage gaps, collaborate with architecture and RTL teams, improve verification methodology, and mentor engineers.

Staff Design Verification Engineer responsible for verifying high-performance out-of-order RISC-V CPU core functionality, especially ALU and integer execution pipelines. Owns verification planning, test development, debug, coverage closure, assertions, scoreboards, and signoff from block through core integration. Partners with architecture and RTL teams to identify microarchitectural risks and improve design quality. The role also contributes reusable automation and methodology while mentoring verification engineers.

Own formal verification for high-performance out-of-order CPU core units from planning through signoff. Develop assertions, properties, harnesses, proof infrastructure, and abstraction strategies; analyze counterexamples, vacuity, over-constraints, and proof failures; and verify pipeline control, ordering, hazards, forward progress, and clock gating. Collaborate with architecture, RTL, and simulation DV teams, improve formal methodology and automation, and mentor engineers.

Own verification of high-performance out-of-order RISC-V CPU cores, with emphasis on vector functionality and microarchitecture. Develop verification plans, environments, checkers, scoreboards, assertions, constrained-random and directed tests, and coverage models. Debug RTL and infrastructure failures, verify RVV behavior and scalar-vector interactions, close coverage gaps, and collaborate with architecture, design, performance, and software teams to achieve signoff quality.

Own formal verification of high-performance out-of-order RISC-V CPU cores from planning through signoff. Develop assertions, properties, checkers, harnesses, abstractions, and proof infrastructure; analyze failures and counterexamples; verify pipeline control, issue and commit logic, load-store ordering, hazards, forward progress, and clock gating. Collaborate with architecture, RTL, and simulation DV teams, improve formal methodology, and mentor engineers.

Lead verification for a cache-coherent interconnect subsystem based on ARM CHI. Develop verification environments, protocol checkers, scoreboards, assertions, coverage models, and constrained-random tests covering coherency, ordering, flow control, retries, and integration. Analyze failures across specifications, RTL, and testbenches; drive verification strategy, coverage closure, methodology improvements, and durable fixes. Collaborate with architecture, design, formal, and software teams while mentoring engineers and supporting signoff.

Identify hardware blocks for formal verification, create test plans and sign-off metrics, build and maintain Chisel-based verification environments, apply formal techniques, debug RTL, automate verification scripts, guide team members, review proofs, and extend assertion libraries. Requires extensive digital hardware formal verification experience, familiarity with VC Formal or JasperGold, HDL knowledge, and an electrical or computer engineering degree.

Drive end-to-end physical design implementation for advanced processor IP, including synthesis, floorplanning, place and route, and signoff. Partner with architecture and RTL teams to optimize timing, power, performance, and area. Diagnose congestion, timing violations, and IR drop; contribute to methodology and automation; lead complex implementation efforts; and mentor junior engineers. The role requires advanced-node tape-out experience and expertise with Synopsys or Cadence physical design and signoff tools.

Lead end-to-end design verification for complex CPU core microarchitecture, including fetch, decode, execution, memory, pipelines, caches, and MMU. Develop SystemVerilog/UVM testbenches, constrained-random tests, scoreboards, checkers, and functional and code coverage models. Create verification plans, drive regressions, debug simulation and emulation failures, validate ISA behavior, test exceptions and interrupts, and achieve coverage and compliance closure with architecture and design teams.

Execute and optimize RTL-to-GDS implementation for high-performance CPU core blocks. Own block-level implementation from synthesis through GDS sign-off, drive timing, power, and area closure, use ML-based design exploration, troubleshoot implementation flows, collaborate with IP and core engineering teams, and develop Tcl/Python automation for repeatable physical design results.

Own RTL-to-GDSII physical design implementation for high-speed System IP, including NoC fabrics, coherent CPU clusters, and memory subsystems. Develop floorplans, close timing on wide high-frequency buses, manage clock distribution, and optimize power, performance, and area on advanced process nodes. Partner with architecture and RTL teams on physical-aware design improvements, and enhance synthesis, place-and-route, sign-off, and automation methodologies.

Lead design verification for complex out-of-order CPU cores and memory subsystems. Own verification strategies, SystemVerilog/UVM testbenches, constrained-random stimulus, assertions, coverage models, debug, and sign-off. Verify core pipelines, caches, TLBs, MMU interfaces, memory ordering, coherence, exceptions, interrupts, and recovery paths. Collaborate with RTL, microarchitecture, performance, and post-silicon teams while mentoring verification engineers and influencing methodology across projects.

Own block- and subsystem-level design verification for out-of-order RISC-V CPU cores. Develop SystemVerilog/UVM testbenches, constrained-random and directed tests, scoreboards, reference models, assertions, and coverage strategies. Verify pipelines, memory systems, caches, TLBs, coherence, speculation, ordering, exceptions, and replay. Analyze regressions, debug complex failures, collaborate with architecture and RTL teams, improve methodology, and mentor junior engineers.

Own block-level RTL-to-GDS implementation for high-performance CPU cores, from synthesis through GDS sign-off. Optimize power, performance, and area on advanced process nodes using Synopsys tools and ML-based design exploration. Develop Tcl and Python automation, troubleshoot timing, power, congestion, and flow issues, and collaborate with IP, methodology, and core engineering teams to achieve physical design closure.

Support end-to-end ASIC physical design for CPU cores, including synthesis, place and route, timing closure, RTL analysis, and PPA optimization. Automate workflows and report analysis using scripting languages, collaborate with RTL and microarchitecture teams, and develop expertise with industry-standard EDA tools while contributing to advanced RISC-V processor products.