Jobs at SiFive

Design and verify digital IPs, CPUs, subsystems and peripherals across VLSI domains. Implement scalable, configurable designs and testbenches. Collaborate with teams, troubleshoot hardware/software interactions, and apply digital electronics, computer architecture, and HDL skills.

Provide senior-level technical escalation and debugging for complex digital physical design issues across the RTL-to-GDSII flow. Guide customers on PD recipes to meet PPA targets, develop reference documentation and application notes, and collaborate with support, account, and R&D teams to improve tools and flows for successful tape-out.

Lead end-to-end physical implementation (RTL2GDS) for IPs: synthesis, floorplan, place-and-route, and signoff. Collaborate with RTL/architecture teams to resolve timing, congestion, and power issues, optimize PPA across product classes, improve flows and mentor junior engineers.

The Senior Accountant is responsible for accounts receivable, general ledger management, month-end closing, fixed asset maintenance, and improving processes. They ensure compliance and accuracy in financial reporting, collaborating with teams to resolve discrepancies and support audits.

The Executive Business Partner / Assistant will support the CTO and EVP Engineering with executive tasks, business operations, strategic support, and communication, managing complex calendars and travel while driving operational efficiency.

Lead power integrity signoff for high-speed CPUs: define IR signoff criteria, architect power grids and bump maps, drive IR drop flow automation, and integrate PrimeTime-PX power readouts while collaborating with Physical Design and Power teams.

The Senior Design Verification Engineer will ensure functional correctness of SoCs/IPs, focusing on verification plans, environment development, debugging, coverage closure, and mentoring junior engineers.

Architect, design and implement features for RISC-V CPU core generators using Chisel, with responsibilities in verification and performance modeling, collaborating with teams.

Design and implement CPU microarchitecture features and ISA extensions using Chisel; integrate into Chisel/FIRRTL framework; perform sandbox verification and collaborate with verification, physical implementation, and performance teams to meet frequency, area, power, and performance goals. Produce documentation and participate in collaborative design.

Improve and debug the RISC-V Linux kernel for high core-count server systems. Engage with upstream Linux and OpenSBI communities to post and review patches. Debug complex software and hardware CPU/SoC issues in emulation and FPGA platforms. Collaborate with system software, validation teams, CPU architects, and RTL engineers to advance core and system designs.

Architect and implement software and firmware for confidential computing on RISC-V/Silicon platforms. Collaborate with CPU/SoC/security teams, implement TEEs, virtualization and peripheral security solutions, write and review hardware/software specifications, and engage customers, partners, and standards bodies to drive platform security.

Design and implement a Visual Studio Code plugin that interfaces with the SCD REST API, build robust responsive front-end UIs, mentor teammates, enforce code quality and automated front-end tests, collaborate with backend, QA, designers, and provide technical leadership for SiFive's Core Designer tooling.

Develop and maintain the high-performance C++ application for an FPGA-hosted hardware emulation framework. Collaborate with FPGA RTL designers, compiler developers, and RISC-V engineers to enable fast, debuggable, and cost-effective emulation for software and hardware co-design.

Manage cross-functional execution of processor core IP programs from scoping through release. Build schedules, track dependencies and risks, drive technical decisions, report status, and improve PM and product lifecycle processes.

The role involves architecting and maintaining the Verification Platform build system, developing tools and build flows, and educating teams on best practices.

The Design Verification Engineer will develop internal processor models and tools, create test cases, and collaborate with teams for verification needs.

Lead the architecture of physical implementation for high-speed CPU designs, focusing on automated ML-driven methodologies and PPA optimization, while interacting with EDA partners.

Develop and maintain core tools for microprocessor design, including simulation and build tools. Requires systems-level programming and tool validation experience.

The role involves designing and implementing CPU cores using RISC-V architecture, collaborating with various teams for verification and optimization, and ensuring high-quality design through documentation and teamwork.

Design and develop system software for RISC-V processors, including Linux kernel, device drivers, OpenSBI, u-boot, and Yocto/OpenEmbedded. Collaborate with architecture and hardware teams, debug complex multicore systems using GDB/JTAG/OpenOCD, and upstream and release open-source and proprietary software.