Jobs at SiFive

Design, develop, upstream and release system software (Linux kernel, device drivers, OpenSBI, U-Boot, Yocto). Collaborate with architecture and hardware teams to integrate hardware features, debug complex multicore systems, and support device interfaces like PCIe, Ethernet, and CXL.

Own release readiness and delivery of SiFive IP customer drops; manage integration/configuration issues across Core/UnCore; generate release collateral and perform quality checks; drive schedule and risk tracking; collaborate with sales/support; debug cross-functionally and improve release automation.

The role involves verifying cache and memory-subsystem functionality, developing verification environments, analyzing failures, and collaborating with design teams.

Join SiFive to optimize and deploy AI models on RISC-V architectures, focusing on heterogeneous computing, inference stack integration, and kernel/compiler synergy.

Design and implement features in RISC-V CPU cores, collaborate with verification and physical design teams, and document processes.

The Senior Software Quality Assurance Engineer will design and optimize CI/CD test automation pipelines, lead root cause analyses of test failures, and define key quality metrics for continuous improvement.

Lead low-power verification and optimization for RISC-V cores, driving quality closure at CPU and block levels. Collaborate with microarchitecture and RTL teams, run UPF/VCS power simulations, develop UVM testbenches, mentor engineers, and support test planning and execution for new features.

Design and verify digital IPs, CPUs, subsystems and peripherals across VLSI domains. Implement scalable, configurable designs and testbenches. Collaborate with teams, troubleshoot hardware/software interactions, and apply digital electronics, computer architecture, and HDL skills.

Design and implement TileLink interconnects, cache controllers, protocol bridges, and other uncore logic as configurable RTL generators (Chisel/Scala). Integrate designs into the Chisel/FIRRTL framework, enable automatic config/verification flows, perform sandbox verification, collaborate with verification teams, and produce documentation.

Design and implement highly-configurable TileLink interconnects, cache controllers, protocol bridges and other uncore RTL generators using Chisel/Scala. Drive performance and coherence improvements, integrate into Chisel/FIRRTL framework, collaborate on verification plans and documentation, and work with teams to deliver high-quality, configurable IP for SoCs.

Lead verification for a scalable cache-coherent interconnect subsystem. Define strategy, develop environments, checkers, assertions and coverage, verify CHI/ACE/CXL/AXI flows, debug root causes, partner with architecture/RTL/formal teams, and mentor engineers to improve verification quality and signoff.

Lead verification for a scalable cache-coherent interconnect subsystem: define strategy and test plans, build verification environments, checkers, assertions and coverage, verify CHI/ACE/CXL/AXI flows, create constrained-random and directed tests, debug across RTL/formal/software, and drive methodology and mentorship to improve verification quality and closure.

Lead physical implementation of high-frequency CPU core blocks from RTL to GDSII. Drive synthesis, place-and-route, timing closure, CTS, and signoff. Collaborate with architecture, RTL, and power teams for aggressive PPA optimization, improve physical design flows and automation, and solve core-specific datapath and congestion challenges.

As a Senior Product Manager, you will articulate SiFive's product portfolio, collaborate with IP architects, and guide Sales during customer engagements. A strong background in product management within the semiconductor industry is required, along with technical marketing and customer interaction experience.

Develop and maintain a Verification Platform for Design Verification. Collaborate with engineers to create reusable testbench components and educate teams on best practices.

Lead and coordinate functional safety programs, managing cross-functional execution, ISO 26262 compliance, risk tracking, and effective communication with stakeholders.

Develop and maintain the Verification Platform, collaborate with engineers to create reusable testbench components, and educate teams on best practices.

Lead verification planning and test strategy for CPU/IP (IOMMU) designs. Develop scalable UVM/SystemVerilog testbenches, write constrained-random stimulus, perform deep RTL debug with waveform tools, drive coverage closure, and integrate third-party VIPs and bus protocols (AXI/AHB/PCIe).

Lead verification planning and testbench development for CPU/RISC-V IP using SystemVerilog and UVM. Create constrained-random tests, write coverage and checkers, debug RTL failures with waveform tools, integrate VIPs, and ensure security-architecture requirements are met.

Lead end-to-end verification of complex CPU core microarchitecture using SystemVerilog/UVM. Develop testplans, testbenches, constrained-random tests, scoreboards, checkers, and coverage models. Validate features (OoO, branch prediction, cache coherency, virtual memory), perform ISA-level compliance (RISC-V/ARM/x86), drive regressions, and debug failures across simulation and emulation platforms.