Search the 55 jobs at SiFive Inc

The role involves leading a team in power convergence and modeling, focusing on power simulation and ASIC power analysis. The candidate will drive projects, utilize scripting skills in Python, Perl, or Tcl, and communicate power status across teams.

Lead the implementation and optimization of SiFive's high-performance Out of Order RISC-V CPUs, collaborating with RTL teams to achieve performance, power, and area goals. Contribute to physical implementation flow and Foundation IP improvements, fostering teamwork and high-quality design in the process.

The Sr. Staff System and Software Architect will design and implement advanced RISC-V computing systems, focusing on both software and hardware architecture. Responsibilities include collaborating with global teams, developing low-level code for operating systems, and writing specifications for new features. This role emphasizes scalability, performance, and cross-functional collaboration in creating innovative computing solutions.

As a Staff Software Engineer, you will architect and implement features and internals for a compiler related to RISC-V, develop tools for the language ecosystem, and design quality code to meet expanding business requirements while interfacing with various teams in SiFive.

The AI/ML Software Engineer will optimize and deploy AI/ML models on RISC-V architectures, develop performance algorithms, and collaborate with hardware engineers. Responsibilities include model profiling, algorithm development, and contributing to open-source projects. Candidates should possess strong programming skills in C/C++ and Python, along with experience in AI/ML development.

The Debug, Trace and Profiling Architect at SiFive will define platform requirements and architectural features for debug, trace, and profiling solutions. They will engage with customers to understand needs, interact with various architectural teams, and develop microarchitecture specifications in a collaborative environment.

The Principal Verification Engineer at SiFive will oversee the verification of RISC-V based CPU IPs, ensuring their functionality and performance. Responsibilities include creating verification strategies, collaborating on microarchitecture design, and resolving verification challenges related to memory subsystems and caches.

The Principal Architect will design scalable SoC architectures, customize chips for various use cases, research emerging needs, and interface with clients to tailor SoCs. Responsibilities include developing multicore platforms and collaborating with Fortune 500 companies on advanced chip designs.

The Staff Engineer DV will architect test methodologies for CPU designs, develop effective verification strategies, create test plans, and build tools and test suites. This role involves collaborating closely with design teams and leading verification efforts to ensure program goals are met.

The Senior Engineer in Design Verification at SiFive will work on low power management and core microarchitecture, lead multiple projects, perform power simulation, and write scripts to assess power impact at various circuit levels. Candidates should possess strong problem-solving skills and adapt well in diverse environments.

Responsible for hands-on CPU verification using SV, UVM, and test generators. Requires 5-10 years of experience in CPU-based verification, proficiency in C and scripting with PYTHON, and knowledge of bus interface protocols.

The Staff Engineer will focus on hands-on System Verilog and UVM development for high-performance CPU verification, including writing test cases, generating targeted tests for RISC-V CPU verification, and working with internal test generators to achieve coverage and test-plan goals.

The role involves leading a team in power convergence and modeling projects, emphasizing experience in AI/ML accelerators or GPUs. The candidate will conduct power simulation, ASIC power analysis, and optimization while scripting in Python, Perl, or Tcl. Strong communication skills are essential for presenting power status to management and product teams.

The Functional Safety Architect will contribute to SiFive's FuSa/RAS solution portfolio, ensuring seamless integration across IPs and collaborating with engineering and product teams to derive requirements for failure detection and response solutions.

The Staff Formal Verification Engineer will implement and maintain formal verification environments, create formal test-plans, and lead the application of various formal verification techniques. Responsibilities include debugging RTL, developing automation scripts, guiding team members, and reviewing proofs with design teams.

The Principal System and Software Architect will design and implement RISC-V computing platforms while collaborating cross-functionally to deliver advanced CPU cores and systems. Responsibilities include developing software for SiFive hardware features, creating architectural specifications, and planning complex projects within a cross-functional engineering team.

The Software Engineer will develop and maintain software applications using Java and Python, enhance data flow scripts, and manage both production and non-production environments. The role includes collaboration with software engineers and business stakeholders in a scrum-based CI/CD environment, focusing on building scalable and resilient applications, as well as dashboard design.

The Senior Software Engineer will implement key business logic and data movement in product design workflows, write automation for development tools, maintain the codebase, and enhance architecture and code quality while interfacing with other teams.

As a FuSa/RAS design engineer, you will architect and implement new features for RISC-V CPU cores, support safety analysis, perform verification, and collaborate with physical design teams while creating high-quality documentation.

The Fusa/RAS Architect will contribute to creating a robust FuSa/RAS solution portfolio, collaborate with engineering teams for optimal implementation, analyze requirements to detect failures, and support product teams to identify customer needs in functional safety and RAS.