Jobs at SiFive

Provides senior technical support for complex semiconductor physical design issues from RTL synthesis through place-and-route and post-route signoff. Responsibilities include debugging EDA tool and implementation problems, optimizing power, performance, and area targets, developing reference flows and technical documentation, and communicating customer feedback to internal engineering and R&D teams.

Lead end-to-end physical implementation of high-speed NoC and Uncore subsystems from RTL to GDSII. Drive architecture and physical-design co-optimization, floorplanning, macro placement, timing closure, routability, clock and reset distribution, and PPA improvements on advanced FinFET nodes. Develop implementation methodologies and automation, solve interconnect challenges, and mentor engineers while partnering with RTL and architecture teams.

Provides customer-facing technical support for SiFive processor IP and datacenter platforms. Resolves software issues involving simulations, toolchains, firmware, operating systems, and hardware development platforms; performs benchmarking and performance analysis; delivers customer training and demonstrations; creates documentation and application notes; and collaborates with engineering, sales, and marketing as a technical escalation point.

Join SiFive to optimize and deploy AI models on RISC-V architectures, focusing on heterogeneous computing, inference stack integration, and kernel/compiler synergy.

Develop high-performance AI/ML software for RISC-V architectures, including compiler infrastructure, runtime systems, model sharding, distributed execution, and performance optimization. Build and optimize LLM and generative AI deployments using MLIR, IREE, Triton, and related frameworks. Collaborate with hardware architects on AI accelerator and microarchitecture co-design, while contributing to open-source compiler and AI/ML projects.

Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.

Lead functional verification for a cache-coherent interconnect subsystem in high-performance SoCs. Develop UVM environments, checkers, scoreboards, assertions, stimulus, and coverage models; verify coherency, ordering, flow control, buffering, QoS, protocols, and integration paths. Create directed and constrained-random tests, debug failures across RTL and verification layers, close coverage gaps, and collaborate with architecture, design, formal, and software teams to improve methodology and verification quality.

Develop and optimize RTL-to-GDS implementation flows for high-performance CPU cores. Drive power, performance, and area closure using timing-driven placement, clock-tree synthesis, routing, and ML-based design-space exploration. Develop Tcl and Python automation, resolve flow and tool issues, support hierarchical physical design, and collaborate with SRAM and standard-cell IP teams. The role requires advanced expertise in Synopsys implementation tools and experience with leading-edge FinFET process nodes.

Own block- and subsystem-level design verification for advanced out-of-order RISC-V CPU cores. Develop SystemVerilog/UVM testbenches, constrained-random and directed tests, reference models, scoreboards, assertions, and coverage strategies. Verify speculative execution, pipelines, memory ordering, caches, TLBs, coherence, exceptions, and flush behavior. Triage regressions, debug complex failures, collaborate with architecture and RTL teams, improve verification methodology, and mentor junior engineers.

Own formal verification strategies for advanced out-of-order CPU cores. Responsibilities include creating formal test plans, implementing Chisel-based verification environments, applying abstraction techniques, debugging RTL failures, automating verification scripts, maintaining assertion libraries, reviewing proofs, and training team members. Requires extensive digital hardware formal verification experience, familiarity with VC Formal or JasperGold, and knowledge of VHDL, Verilog, or SystemVerilog.

Own CPU verification planning and execution for ALU, floating-point, vector, and datapath blocks. Develop formal and simulation-based verification environments, assertions, checkers, scoreboards, stimulus, and coverage models. Drive debug, coverage closure, and verification strategy for dependencies, forwarding, replay, exceptions, flush/recovery, and execution-to-commit behavior. Collaborate with architecture, design, and verification teams while improving reusable verification methodologies and automation.

Define end-to-end formal verification strategies for complex SoCs and IP subsystems. Identify high-risk architectural issues, develop formal methodologies, manage abstractions, drive proof convergence, and improve implementations for correct-by-construction designs. Lead verification across large hardware systems, including CPU microarchitecture, communication fabrics, and protocols, using formal methods and simulation co-verification.

Own verification planning and execution for RISC-V CPU Vector, ALU, and floating-point units. Develop SystemVerilog/UVM testbenches, tests, assertions, checkers, scoreboards, stimulus, and coverage models. Verify arithmetic, dependencies, forwarding, replay, exceptions, and execution-to-commit behavior. Perform debug, coverage closure, and root-cause analysis while collaborating with architecture, design, and verification teams. Improve reusable verification methodologies and automation for future CPU programs.

Develop formal verification plans and properties for RISC-V processors and Chisel-based digital designs. Build verification environments using Chisel, Scala, and Tcl; apply assertion-based, model-checking, equivalence-checking, coverage, and constrained-random methodologies. Analyze formal results, debug failures, improve verification flows, and collaborate with design engineers on architecture and correctness.

Analyzes and optimizes SiFive IP power consumption across architecture, logic, circuit, RTL, and silicon levels. The role develops power models, correlates them with RTL and silicon results, guides performance-power tradeoffs for high-performance out-of-order CPUs, and improves power analysis workflows. Candidates need advanced computer architecture education, 5+ years of power benchmarking and ASIC optimization experience, and strong problem-solving skills.

Own verification planning, execution, debugging, coverage closure, and methodology for high-performance out-of-order RISC-V CPU core components. Develop SystemVerilog and UVM environments, assertions, scoreboards, stimulus, and coverage models. Partner with architecture and RTL teams to identify risks, resolve microarchitectural issues, and achieve signoff quality across frontend, midcore, load-store, execution, vector, and hardware prefetch units. Mentor engineers and improve verification infrastructure and practices across future CPU generations.

Own functional verification for high-performance out-of-order RISC-V CPU core units from block level through core integration. Develop test plans, UVM environments, testbenches, checkers, scoreboards, assertions, constrained-random tests, and coverage models. Debug failures, identify RTL and verification issues, close coverage gaps, and collaborate with architecture, design, performance, and software teams. Contribute reusable verification infrastructure and methodology for future CPU generations.

Staff Design Verification Engineer responsible for planning and executing verification for high-performance out-of-order RISC-V CPU cores, including vector functionality and microarchitectural interactions. Develops verification environments, checkers, scoreboards, assertions, stimulus, and coverage models; leads debug and coverage closure; partners with architecture and design teams; improves verification methodology; and mentors engineers.

Own formal verification for high-performance out-of-order RISC-V CPU cores, including planning, assertions, proof strategies, abstraction, debugging, and signoff closure. Develop scalable formal environments and infrastructure for control, ordering, pipeline, load-store, clock-gating, and microarchitectural behavior. Analyze failures and coverage gaps, collaborate with architecture and RTL teams, improve verification methodology, and mentor engineers.

Staff Design Verification Engineer responsible for verifying high-performance out-of-order RISC-V CPU core functionality, especially ALU and integer execution pipelines. Owns verification planning, test development, debug, coverage closure, assertions, scoreboards, and signoff from block through core integration. Partners with architecture and RTL teams to identify microarchitectural risks and improve design quality. The role also contributes reusable automation and methodology while mentoring verification engineers.