Jobs at SiFive

Lead design verification for out-of-order CPU cores: own DV strategy and execution, architect SystemVerilog/UVM testbenches, develop constrained-random and scenario libraries, define coverage and assertion sign‑off, debug complex OOO and memory/coherence issues, collaborate with RTL/microarchitecture/post‑silicon teams, and mentor junior DV engineers.

Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.

The AI/ML Software Engineer will optimize and deploy LLMs and Generative AI models on RISC-V architectures, developing compiler stacks, runtime systems, and performance optimization strategies while collaborating with hardware architects.

Seeking a skilled Verification Engineer for CPU core microarchitecture verification, covering DV strategy, architecture validation, and closure for high-performance processors.

Lead selection and formal verification of digital blocks: create formal test plans, implement and maintain FV environments in Chisel, apply abstraction techniques, debug RTL, automate verification, review proofs, and mentor teammates.

The Performance Architect will analyze performance bottlenecks in CPU microarchitecture, implement performance models, and optimize workloads for high-performance AI and out-of-order CPUs.

The intern will join the Design Verification Infrastructure team to develop and maintain the Verification Platform, enhancing design verification technologies through collaboration and software development in Scala and Python.

Design, specify and implement arithmetic operators for RISC-V instructions (floating-point, vector, crypto, integer), optimize timing/area/power, create unit and formal tests, collaborate with physical implementation teams, and produce high-quality documentation.

The Staff Design Verification Engineer drives the verification of cache-coherent interconnect subsystems, focusing on CXL protocols and integration, defining verification plans, and improving overall verification quality through collaboration and mentorship.

Develop and maintain performance benchmarking and regression infrastructure for SiFive and competitor boards (including FPGA cores); enable boards, run system benchmarking across embedded Linux environments, root-cause SW/HW performance gaps, support customer benchmarking, build workflows, and analyze competitor microarchitectures.

Lead formal verification for NoC and interconnect blocks: develop verification plans and SVA property sets, build reusable formal environments, debug proofs and counterexamples, collaborate with design and simulation teams, and improve verification methodology for scalable interconnect verification and signoff.

Develop and execute verification plans for NoC and coherent interconnect IP/subsystems. Build UVM/SystemVerilog testbenches, assertions, checkers, scoreboards, and coverage. Verify NoC topologies, routing, protocols, and subsystem integration with memory fabrics and cache coherency. Debug simulations, drive closure with RTL teams, track coverage/metrics, and develop reusable VIP/DV components.

The role involves implementation of NoC and Uncore systems, focusing on PPA optimization. Key responsibilities include leading physical design, driving co-design across levels, and mentoring junior engineers.

The Principal Design Verification Engineer will lead verification strategies, execute high-performance CPU subsystem verification, and improve methodologies, with a focus on CPU core and coherent interconnect verification.

As a Staff Physical Design Engineer, own the physical design of memory cache structures, drive optimizations, solve bottlenecks, and improve methodologies while collaborating with cross-functional teams.

The Staff Design Verification Engineer will lead verification for a cache-coherent interconnect subsystem, focusing on verification planning, execution, and improving methodologies. Key responsibilities include developing robust verification environments and addressing complex verification problems.

The Senior Accountant is responsible for accounts receivable, general ledger management, month-end closing, fixed asset maintenance, and improving processes. They ensure compliance and accuracy in financial reporting, collaborating with teams to resolve discrepancies and support audits.

Lead the Low Power Verification and Formal Equivalence methodologies, ensuring robust power intent and logical equivalence throughout RTL-to-GDSII flow.

The Senior Design Verification Engineer will ensure functional correctness of SoCs/IPs, focusing on verification plans, environment development, debugging, coverage closure, and mentoring junior engineers.

Design, develop, upstream and release system software (Linux kernel, device drivers, OpenSBI, U-Boot, Yocto). Collaborate with architecture and hardware teams to integrate hardware features, debug complex multicore systems, and support device interfaces like PCIe, Ethernet, and CXL.