Jobs at SiFive

Develop and maintain formal verification environments for digital hardware blocks using Chisel and industry-standard formal tools. Create test plans, define properties and sign-off metrics, apply abstraction techniques, debug RTL failures, automate verification scripts, review proofs with design teams, maintain assertion libraries, and train team members on formal verification practices.

Own verification strategy and execution for complex CPU, SoC, and IP blocks from architecture through tape-out. Architect SystemVerilog/UVM testbenches, develop constrained-random and coverage-driven environments, apply assertions and formal verification, lead debug and coverage closure, and improve regression infrastructure. Provide technical leadership, mentor engineers, review verification plans, and collaborate with architecture, RTL design, software, validation, and post-silicon teams.

Own design verification strategy and execution for out-of-order RISC-V processor cores and cache/memory subsystems through tape-out. Architect UVM testbenches, create constrained-random tests, develop scoreboards and protocol checkers, drive functional and code coverage closure, apply assertions and formal verification, debug complex ordering and coherence issues, and mentor junior engineers while collaborating across architecture, RTL, software, and post-silicon teams.

Own block- and subsystem-level design verification for out-of-order CPU cores. Develop SystemVerilog/UVM testbenches, constrained-random tests, scoreboards, reference models, assertions, and coverage strategies. Verify execution pipelines, memory systems, caches, TLBs, coherence, memory ordering, exceptions, and speculative execution. Debug regressions, triage failures, collaborate with architecture and RTL teams, improve verification methodology, and mentor junior engineers.

Own end-to-end verification of CPU core components and microarchitectural features, including out-of-order execution, branch prediction, cache coherency, virtual memory, RAS, and functional safety. Develop SystemVerilog/UVM testbenches, constrained-random tests, scoreboards, checkers, and coverage models. Drive regressions, debug simulation and emulation failures, validate ISA behavior, and achieve coverage closure in collaboration with architecture and design teams.

Develop and maintain SiFive’s verification platform infrastructure, libraries, tools, and methodologies for design verification. Build functionality using Chisel and CIRCT, create Scala-based verification libraries and generators, and develop Python tools for querying design intent and metadata. Collaborate with platform technology teams, support end-to-end verification flows, and educate teams on best practices. The role requires compiled and scripting language experience, modern software engineering knowledge, and experience deploying production software.

Develops and deploys power analysis flows, models, and measurement infrastructure for SiFive processor IP. The role correlates power models with RTL and silicon, supports architecture exploration, and optimizes ASIC power across architecture, logic, and circuit levels. It requires advanced computer architecture knowledge, particularly high-performance out-of-order CPUs, along with software engineering practices for maintaining large object-oriented codebases.

Analyze and benchmark SiFive IP power consumption, correlate power models with RTL and silicon, work with architects and designers to optimize power/performance trade-offs, and innovate improvements to power analysis flows.

The role involves analyzing and optimizing power consumption in SiFive IP, guiding architecture for power efficiency, and improving power analysis flows.

Develop and deploy methodologies for measuring and analyzing power consumption of SiFive IPs. Guide teams in designing energy-efficient IPs through power modeling and analysis.

Design and implement CPU power management, reset, and clocking solutions. Collaborate with teams to verify and optimize designs based on RISC-V architecture.

Ownership of AWS EKS infrastructure and CI/CD pipelines (Terraform, GitHub Actions, Concourse, Jenkins). Implement observability, automation with Python, and maintain Docker/Helm deployments. Secondary focus on building scalable Django/Python backend APIs, PostgreSQL optimization, and integrating AWS services (SQS, S3, Lambda).

Lead CPU subsystem verification by defining strategy, building UVM/SystemVerilog testbenches, creating constrained-random and assembly tests, debugging RTL/SOC issues, and mentoring junior engineers.

Lead physical implementation of high-frequency CPU core blocks from RTL to GDSII. Drive synthesis, place-and-route, timing closure, CTS, and signoff. Collaborate with architecture, RTL, and power teams for aggressive PPA optimization, improve physical design flows and automation, and solve core-specific datapath and congestion challenges.

Lead verification for a scalable cache-coherent interconnect subsystem: define strategy and test plans, build verification environments, checkers, assertions and coverage, verify CHI/ACE/CXL/AXI flows, create constrained-random and directed tests, debug across RTL/formal/software, and drive methodology and mentorship to improve verification quality and closure.

Lead verification for a scalable cache-coherent interconnect subsystem. Define strategy, develop environments, checkers, assertions and coverage, verify CHI/ACE/CXL/AXI flows, debug root causes, partner with architecture/RTL/formal teams, and mentor engineers to improve verification quality and signoff.

As a Senior Product Manager, you will articulate SiFive's product portfolio, collaborate with IP architects, and guide Sales during customer engagements. A strong background in product management within the semiconductor industry is required, along with technical marketing and customer interaction experience.

Lead low-power verification and optimization for RISC-V cores, driving quality closure at CPU and block levels. Collaborate with microarchitecture and RTL teams, run UPF/VCS power simulations, develop UVM testbenches, mentor engineers, and support test planning and execution for new features.

Design and implement features in RISC-V CPU cores, collaborate with verification and physical design teams, and document processes.

Design and implement highly-configurable TileLink interconnects, cache controllers, protocol bridges and other uncore RTL generators using Chisel/Scala. Drive performance and coherence improvements, integrate into Chisel/FIRRTL framework, collaborate on verification plans and documentation, and work with teams to deliver high-quality, configurable IP for SoCs.