Jobs at SiFive

Leads software product strategy, roadmap, and developer experience for SiFive’s datacenter semiconductor IP portfolio. Owns SDKs, toolchains, firmware, operating-system enablement, drivers, and developer tools; translates customer and ecosystem needs into product requirements and release plans. Partners across engineering, architecture, sales, customers, cloud providers, and open-source communities to support silicon milestones, deployments, adoption, launches, and strategic programs.

Own formal verification for out-of-order CPU core blocks, including test planning, property development, abstraction, proof, debugging, sign-off, assertion library maintenance, and automation. Collaborate with micro-architects, RTL designers, and verification teams while guiding colleagues on formal verification tools and techniques.

Verify high-performance out-of-order RISC-V CPU cores from RTL bring-up through tapeout. Responsibilities include developing UVM testbench infrastructure, constrained-random and directed tests, functional coverage, assertions, regression tooling, and co-simulation flows. Debug pipeline, memory-ordering, speculation, and privilege-related failures using logs and waveforms, drive coverage closure, maintain regression health, and collaborate with micro-architects and RTL designers on verification plans and issues.

Owns formal verification strategies for complex processor modules, including identifying suitable blocks, creating test plans, implementing Chisel-based verification environments, applying formal techniques, debugging RTL, automating verification, maintaining assertion libraries, and guiding team members. Requires extensive digital hardware formal verification experience, familiarity with VC Formal or JasperGold, and knowledge of VHDL, Verilog, and SystemVerilog.

Own verification strategy and execution for out-of-order CPU cores and cache/memory subsystems from architecture through tape-out. Architect UVM testbenches, create test plans, develop scoreboards and protocol checkers, drive coverage closure, apply assertions and formal verification, debug complex pipeline, ordering, coherence, and TLB issues, and mentor junior engineers. Collaborate with architecture, RTL, software, performance, and post-silicon teams.

Develop and execute SystemVerilog/UVM verification for high-performance RISC-V CPUs. Create test cases, use test generators, target coverage and test-plan scenarios, and integrate third-party verification IP. Apply CPU architecture and microarchitecture knowledge, object-oriented programming, scripting, and bus-interface expertise including AXI or PCIe.

Leads end-to-end design verification for complex CPU cores, including microarchitecture validation, test planning, coverage closure, constrained-random testing, testbench development, scoreboarding, regression, and failure debug. Validates features such as out-of-order execution, branch prediction, cache coherency, virtual memory, RAS, and functional safety. Partners with architecture and design teams on ISA compliance, exceptions, interrupts, and silicon-level quality.

Develop and verify high-performance RISC-V CPUs using SystemVerilog and UVM. Responsibilities include writing test cases, using test generators, targeting coverage and test-plan scenarios, integrating third-party bus VIPs, and applying CPU architecture and microarchitecture knowledge. The role also involves scripting, object-oriented programming, and verification of interfaces such as AXI or PCIe.

Lead verification and optimization of RISC-V low-power profiles using UPF, drive CPU and block-level quality closure, collaborate with microarchitecture and RTL teams on power flows, and participate in test planning and execution. Provide technical leadership and mentorship while supporting multiple projects. Develop UVM test benches, perform power simulation with VCS and UPF, and use Python, Perl, or Tcl for scripting.

Lead design verification and optimization for RISC-V low-power profiles using UPF, drive CPU and block-level quality closure, develop UVM testbenches, conduct power simulations, collaborate with architecture and RTL teams, and mentor junior engineers. The role also involves test planning, execution, scripting, power-impact analysis, and leading multiple projects.

Lead verification for a cache-coherent interconnect subsystem based on ARM CHI. Develop verification environments, protocol checkers, scoreboards, assertions, coverage models, and constrained-random tests covering coherency, ordering, flow control, retries, and integration. Analyze failures across specifications, RTL, and testbenches; drive verification strategy, coverage closure, methodology improvements, and durable fixes. Collaborate with architecture, design, formal, and software teams while mentoring engineers and supporting signoff.

Leads functional safety and reliability work for processor and SoC platforms across automotive, robotics, AI, and data center applications. Owns safety requirements, goals, traceability, risk analysis, verification, assessments, audits, certification, and customer support. Applies ISO 26262, FMEDA, fault modeling, diagnostic coverage, safety cases, and fault injection. Coordinates architecture, design, verification, software, quality, product, program management, and customer-facing teams while addressing RAS mechanisms and technical risks.

Own formal verification strategies for advanced out-of-order CPU cores. Responsibilities include creating formal test plans, implementing Chisel-based verification environments, applying abstraction techniques, debugging RTL failures, automating verification scripts, maintaining assertion libraries, reviewing proofs, and training team members. Requires extensive digital hardware formal verification experience, familiarity with VC Formal or JasperGold, and knowledge of VHDL, Verilog, or SystemVerilog.

Own end-to-end verification of CPU core components and microarchitectural features, including out-of-order execution, branch prediction, cache coherency, virtual memory, RAS, and functional safety. Develop SystemVerilog/UVM testbenches, constrained-random tests, scoreboards, checkers, and coverage models. Drive regressions, debug simulation and emulation failures, validate ISA behavior, and achieve coverage closure in collaboration with architecture and design teams.

Develop and maintain a scalable Verification Platform including VIPs, AIPs, and testbench components. Architect libraries in Scala/Chisel, build SystemVerilog/UVM VIPs, create test plans and testbenches, and educate DV teams on best practices.

Lead design verification for complex out-of-order CPU cores and memory subsystems. Own verification strategies, SystemVerilog/UVM testbenches, constrained-random stimulus, assertions, coverage models, debug, and sign-off. Verify core pipelines, caches, TLBs, MMU interfaces, memory ordering, coherence, exceptions, interrupts, and recovery paths. Collaborate with RTL, microarchitecture, performance, and post-silicon teams while mentoring verification engineers and influencing methodology across projects.

Develop and maintain the Verification Platform, collaborate with engineers to create reusable testbench components, and educate teams on best practices.

Lead end-to-end design verification for complex CPU cores, including fetch, decode, execution, memory, pipelines, caches, and MMUs. Develop verification strategies, test plans, UVM testbenches, constrained-random tests, scoreboards, checkers, and functional/code coverage models. Validate out-of-order execution, branch prediction, cache coherency, virtual memory, paging, exceptions, interrupts, and ISA compliance. Drive regressions, debug simulation and emulation failures, and partner with architecture and design teams to achieve verification closure.

Develop and maintain a Verification Platform for Design Verification. Collaborate with engineers to create reusable testbench components and educate teams on best practices.

Owns Workday configuration, enhancements, reporting, security, workflows, integrations, testing, releases, and optimization across Recruiting, Compensation, Performance, Benefits, and HCM. Partners with HR, IT, Finance, Payroll, vendors, and business leaders to translate requirements into scalable solutions, troubleshoot issues, maintain documentation, support global operations, and improve system performance, data quality, security, and user experience.