Company Overview
Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.
Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.
Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.
We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.
At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.
If that's you, join us — the intelligence everywhere revolution starts here.
Responsibilities
- Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.
- Develop and implement low-power DFT architecture and infrastructure.
- Generate structural test vectors, analyse, and improve coverage, test time and test cost.
- Perform pre/post-layout scan and MBIST simulations.
- Work with designers on STA, physical, power and logical issues related to DFT.
- Work with test engineers to bring up test vectors on silicon.
Qualifications
- BS/MS in ECE/EE and at least 10 years of experience in DFT implementation.
- Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST.
- Experience in creating and implementing hierarchical DFT architecture in complex SoC.
- Experience in Low-Power DFT and MBIST.
- Experience in test time and test coverage analysis for scan and MBIST patterns.
- Experience in working with test engineering team to bring up production test program.
- Extensive knowledge of timing concepts and constraint development.
- Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments.
- Experience in RTL is required.
- Experience in scripting like Tcl is preferred.
- Experience with GLS (gate level simulation) is preferred.
- Motivated, self-driven engineer with attention to detail.
- Strong verbal and written English communication skills.
Skills Required
- BS/MS in ECE/EE
- At least 10 years of experience in DFT implementation
- Skilled in DFT structures including scan, boundary scan, and MBIST
- Experience in low-power DFT and MBIST
- Experience with test time and coverage analysis
- Extensive knowledge of timing concepts and constraint development
- Experience developing scan ATPG and MBIST test benches
- Experience in RTL
- Experience in scripting like Tcl
- Experience with gate level simulation (GLS)
What We Do
Ambiq® enables intelligence (AI and beyond) everywhere by delivering the lowest-power semiconductor solutions for battery-powered edge devices. As a pioneer in ultra-low power SoCs, Ambiq empowers wearables, IoT, smart home, healthcare, and industrial products with always-on, energy-efficient intelligence. Backed by our SPOT® technology and global innovation leadership, Ambiq is shaping the future of edge AI.
Why Work With Us
Direct influence on silicon architecture Smaller, high-impact teams Hardware/software co-design in real time Faster technical decision cycles Visible ownership at Staff & Director level Austin-based collaboration culture
Ambiq Offices
OnSite Workspace
Building silicon and embedded AI systems requires tight collaboration across firmware, hardware, validation, and architecture teams. We believe the hardest engineering problems are solved through direct, daily collaboration.
