Jobs at Ambiq

Provides technical leadership for embedded MCU software development focused on Secure Boot ROM, secure bootloaders, SDK security, cryptographic operations, HAL, and BSP development. Leads security feature implementation from design through production, including FPGA and silicon testing, debugging, automated testing, and cross-functional collaboration. Requires deep expertise in ARM architectures, bare-metal and RTOS systems, embedded security, C/C++, Python, and low-level hardware/software debugging.

Leads architecture, specification, transistor-level design, verification, layout supervision, validation, and production release of complex analog and mixed-signal IC subsystems. The role addresses power management, clocking, data conversion, advanced-node design, manufacturing test, and post-silicon characterization. It also guides senior engineers, leads technical reviews, resolves cross-functional issues, and supports product development and customer problem resolution.

Supports low-power DFT implementation and verification for SoC designs, including scan insertion, scan-chain verification, MBIST, rule checking, test-coverage analysis, and debugging. Develops Tcl, Python, and Shell scripts for automation, documents methodologies and results, and collaborates with RTL, DFT, design verification, and physical design engineers.

Explore AI/ML-assisted and self-adaptive memory design techniques for optimizing performance, power efficiency, robustness, and yield. Analyze memory assist methods, operating conditions, failure signatures, and process variations. Develop adaptive monitoring, prediction, voltage, timing, and read/write control techniques, then document, benchmark, and present the proposed architecture and design insights.

Design Verification Intern responsible for verifying digital and SoC designs. Develop test plans, reusable SystemVerilog/UVM testbenches, test cases, stimulus, checkers, and coverage metrics. Automate randomized testing, debug verification issues, perform root-cause analysis, and collaborate with design teams. The role focuses on semiconductor and IoT applications, with edge AI inference experience preferred.

Supports foundation IP development for edge AI SoCs through standard-cell circuit design, simulation, layout, characterization, and debugging. Uses Python, pandas, and scikit-learn to analyze timing, power, noise, and process-voltage-temperature data, identify outliers, and build predictive models that reduce simulation effort. The intern also performs DRC/LVS cleanup, investigates simulation mismatches, and documents findings for the IP team.

Supports block-level physical implementation for ultra-low-power SoC designs, including floorplanning, placement, clock tree synthesis, routing, timing closure, static timing analysis, power and signal integrity analysis, DRC/LVS closure, and automation scripting. Collaborates with RTL, verification, and physical design engineers while documenting results and learning industry-standard semiconductor design workflows.

Develop and test the Ambiqsuite SDK for Ambiq SoC devices and emulation platforms. Extend HALs, BSPs, and device drivers for new MCU platforms; create SDK examples and reliability test cases; investigate issues and propose solutions; and build Python automation scripts for SDK development, builds, and verification.

Own revenue and product margin planning, forecasting, and budget-to-actual analysis for semiconductor products and manufacturing operations. Build financial models and R&D investment business cases, including ROI, payback, and sensitivity analyses. Partner with Sales, Marketing, R&D, Manufacturing, Operations, Accounting, and executives to optimize margins, prioritize investments, explain financial performance, and support investor relations. The role includes periodic travel to Taiwan and occasional late-night calls.

Leads physical implementation of analog IC subsystems including PMUs, clocking, and data converters. Responsibilities include floorplanning, transistor-level layout, matching, shielding, parasitic extraction, LVS/DRC closure, tape-out, validation, production test support, and layout review. Collaborates with analog, digital, RTL, physical design, product, and applications engineering teams. This is an onsite role requiring five days per week.

Leads specification, architecture, transistor-level design, verification, layout supervision, validation, and manufacturing test for complex analog IC subsystems. Partners with architecture, RTL, product, applications, and marketing teams; resolves cross-block issues; supports customer and manufacturing challenges; and mentors senior engineers without formal management responsibility.

Leads the analog design organization and sets architecture, specifications, methodology, and technical direction across multiple semiconductor programs. Directly designs or supervises critical transistor-level analog blocks, oversees verification, validation, layout, and production bring-up, and resolves high-risk technical issues. The role also mentors and manages engineers, chairs design reviews, partners with digital and product teams, supports customer and executive discussions, and drives improvements in tools, design flow, and IP reuse.

Lead system architecture for next-generation ultra-low-power AI SoCs from concept through production. Define processor, memory, interconnect, clocking, power, accelerator, and hardware/software partitioning strategies while managing power, performance, and area tradeoffs. Develop architecture specifications and models, evaluate IP, guide silicon implementation and validation, collaborate with customers and cross-functional engineering teams, and mentor architecture staff.

Responsible for post-silicon validation and characterization of analog and mixed-signal SoC subsystems. Develop validation plans, automate testing and data analysis, characterize silicon across process, voltage, and temperature, analyze performance, correlate results with simulation and production data, and debug analog, digital, firmware, power, and board-level interactions. The role also supports validation hardware, lab infrastructure, test coverage, yield improvement, and production readiness.

Develop and support embedded software for Ambiq SoCs, including drivers, HAL updates, board support packages, example applications, Zephyr enablement, debugging tools, and test software. Collaborate with hardware, software, field engineering, and customers to resolve complex system-level issues. Support evaluation platforms, customer applications, and silicon debug while producing application notes, knowledgebase content, and software design guidelines.

Designs and develops PCB-based evaluation hardware for low-power, ARM-based SoCs. Responsibilities include hardware architecture, schematic and layout design, system bring-up, lab debugging, manufacturing test development, customer hardware reviews, issue resolution, embedded software support, and creation of application notes and hardware design guidelines.

Own end-to-end digital design verification for complex SoCs at block, subsystem, and full-chip levels. Develop UVM/SystemVerilog testbenches, verification plans, constrained-random and directed tests, scoreboards, coverage models, and C/C++ SoC validation libraries. Automate regressions and reporting, debug failures, perform root-cause analysis, and collaborate with architecture, design, and software teams. The role requires managing verification milestones, risks, and deliverables through multiple successful tape-outs.

The Field Application Engineer supports global customers by aiding in the design-in process of Ambiq's low-power semiconductor solutions, optimizing energy efficiency, and developing hardware and software for embedded systems. Responsibilities include design reviews, customer collaboration, debugging, and presenting complex technical topics.

The Senior Staff SoC Power and Performance Architect role focuses on advancing ultra-low-power semiconductor solutions for AI edge, wearable, medical device, and IoT applications. The position is based onsite five days per week in Austin and appears intended to lead SoC power and performance architecture in collaboration with cross-functional engineering and product teams. Detailed responsibilities and qualifications were not provided in the posting.

Lead and scale Ambiq's silicon validation organization, define post-silicon validation strategy and automation, drive bring-up, characterization, debug, and production correlation, build global teams and lab infrastructure, manage priorities across concurrent programs, and provide technical leadership for complex silicon issues and customer escalations.