Jobs at Ambiq

The Product Manager drives profitability by improving product yield and performance, managing engineering projects, and collaborating with cross-functional teams to resolve product issues.

Lead transistor-level analog IC design from specification through layout, verification, prototype testing and production support. Define chip/block specs, architect circuits, supervise layout, run design reviews, interface with digital designers, develop manufacturing test plans, and support product, marketing, and applications engineering.

As Head of Post-Silicon Engineering, define strategies for low-power MCUs, lead validation, manage global engineering teams, and engage with customers for product development.

Develop, extend, and test secure bootrom/bootloader and related SDK components for Apollo SoC. Perform pre-silicon FPGA emulation, post-silicon bring-up, cryptographic hardware-accelerated testing, HAL/BSP implementation, and collaborate on test automation and security verification.

The Senior Embedded Graphics Software Engineer develops and maintains GPU software stacks, collaborates on graphics APIs, and supports pre- and post-silicon testing.

Lead end-to-end production planning and capacity optimization for wafer fabrication, assembly, and test. Monitor WIP, coordinate with foundries/OSATs, maintain ERP data, build Excel simulations, define safety stock, and resolve supply chain risks to ensure on-time delivery.

The Staff Engineer - DFT will implement DFT strategies for low-power SoCs, develop test architectures, and collaborate with teams for test vector integration and analysis.

Lead physical implementation of SoCs from netlist to GDS: floorplanning, placement, CTS, routing, verification, and DFM. Drive timing, IR/EM, and signal integrity closure, improve flows and scripts, and collaborate with front-end, DFT, ARC, and package teams using Cadence/Synopsys toolflows for FinFET and multi-patterning processes.

The Senior Embedded Software Engineer will develop, integrate, and verify SDKs for SoC platforms, lead HAL and driver development, and validate embedded systems through collaboration across teams.

Lead end-to-end timing methodology and signoff for SoCs: define flows, constraints, and PVTR corners; drive block-to-SoC timing closure and pre-/post-silicon correlation; perform extraction, glitch/noise and power/timing tradeoff analysis; automate STA workflows and collaborate with RTL, DFT, PnR, IP, bring-up, and validation teams.

Lead end-to-end digital verification for complex SoCs, developing UVM/SystemVerilog testbenches, SoC-level C/C++ tests, automation, coverage goals, debugging, and collaborate with design teams to ensure production-ready silicon.

The Field Application Engineer will support global customers in design-in activities, develop product solutions, optimize power consumption, and assist with customer HW/SW development.

The Field Application Engineer supports global customers by aiding in the design-in process of Ambiq's low-power semiconductor solutions, optimizing energy efficiency, and developing hardware and software for embedded systems. Responsibilities include design reviews, customer collaboration, debugging, and presenting complex technical topics.

Design, train, optimize, and deploy efficient on-device ML models (audio and vision) for resource-constrained products; maintain Ambiq ADKs; port and optimize customer models; apply model-efficiency techniques; produce customer-facing demos, docs, and benchmarks.

Design and implement low-power DFT architecture for ultra-low-power SoCs: scan insertion, boundary scan, MBIST and ATPG; generate and optimize structural test vectors; run pre/post-layout simulations; collaborate with designers and test engineers to resolve timing, power, and logical issues and bring up tests on silicon.

Define, design, and implement system-level tests and automation for ARM Cortex-M, DSP, and NPU platforms. Develop firmware test frameworks in C/assembly and automation in Python, perform pre- and post-silicon validation on FPGA/emulation and silicon, debug across software and hardware layers, measure performance, and mentor junior engineers.

Lead and scale the physical implementation organization for ultra-low-power MCU products. Define strategy, build and mentor teams, oversee full-chip and block-level physical design (floorplanning, power planning, CTS, P&R, timing closure, DRC/LVS, EM/IR signoff), collaborate cross-functionally, manage schedules and tape-out readiness, and ensure first-silicon success and manufacturability.

Lead timing methodology and closure for block and SoC levels in modern FinFET/multi-patterning processes. Define flows, constraints, signoff correlation, timing margining, glitch noise analysis, and collaborate with RTL, PnR, DFT, and post-silicon teams to achieve timing convergence and best-in-class PPA.

Lead end-to-end memory deployments: define memory roadmap, evaluate and simulate memory architectures (SRAM/DRAM/HBM/RRAM/MRAM), lead characterization, work with architects, circuit and process teams, and third-party vendors to ensure energy-efficient, high-yield memory integration.

Lead software architecture for low-power Edge AI MCUs: define requirements, perform functional allocation, prototype, guide implementation and testing, optimize performance/power, enforce standards, and mentor engineers.