Jobs at Ambiq Micro

Design, implement, and optimize Ambiq's embedded AI runtimes and operator libraries for on-device inference. Build profiling, benchmarking, and regression tests; optimize latency, memory, and energy on constrained hardware; support customer integrations across bare metal and RTOS toolchains; and maintain docs, tooling, and upstream/fork health.

Responsible for verifying digital and mixed-signal designs, developing test plans, executing SoC-based verification, and automating test environments.

The role involves building and optimizing embedded AI runtimes, implementing ML operator kernels, and improving performance for on-device AI in resource-constrained environments.

The Sr Multimedia Architect will define low-power SoC multimedia specifications, collaborate with cross-functional teams, and oversee integration and validation processes for embedded systems targeting wearable and IoT devices.

Lead the development and testing of Ambiq's Zephyr software, including driver and software testcase development, maintaining compliance, and solving issues in collaboration with global teams.

The Principal Embedded Software Architect will design the software architecture for low-power Edge AI MCUs, leading decisions for functionality and performance, partnering with hardware teams, and mentoring engineers.

The Sr. Director of Front End Engineering will drive innovation in semiconductor solutions, oversee engineering teams, and ensure project success with customer-centric solutions.

Lead the development of the GPU software stack for Ambiq's MCU platforms, defining GPU HAL, implementing graphics APIs, and conducting silicon bring-up.

The Senior Embedded Graphics Software Engineer develops and maintains GPU software stacks, collaborates on graphics APIs, and supports pre- and post-silicon testing.

The Staff Engineer - DFT will implement DFT strategies for low-power SoCs, develop test architectures, and collaborate with teams for test vector integration and analysis.

The Senior Embedded Software Engineer will develop, integrate, and verify SDKs for SoC platforms, lead HAL and driver development, and validate embedded systems through collaboration across teams.

Lead and own design verification for digital and mixed-signal SoCs. Develop test plans, build SystemVerilog/UVM reusable testbenches, write C-based test packages, run full-chip/module verification, implement CPF/UPF power-aware flows, automate randomized testing and scoreboarding, debug and perform root-cause analysis, and track coverage and verification metrics while collaborating with design and software teams.

Design, train, optimize, and deploy efficient on-device ML models (audio and vision) for resource-constrained products; maintain Ambiq ADKs; port and optimize customer models; apply model-efficiency techniques; produce customer-facing demos, docs, and benchmarks.

Lead design and implementation of HAL, device drivers, RTOS ports, and test cases for NPU, DMA/DME, and memory subsystems. Support pre-/post-silicon bring-up, verification, performance optimization, debugging, and cross-team/customer support.

Design and implement low-power DFT architecture for ultra-low-power SoCs: scan insertion, boundary scan, MBIST and ATPG; generate and optimize structural test vectors; run pre/post-layout simulations; collaborate with designers and test engineers to resolve timing, power, and logical issues and bring up tests on silicon.

Define, design, and implement system-level tests and automation for ARM Cortex-M, DSP, and NPU platforms. Develop firmware test frameworks in C/assembly and automation in Python, perform pre- and post-silicon validation on FPGA/emulation and silicon, debug across software and hardware layers, measure performance, and mentor junior engineers.

Lead development and testing of Ambiq's embedded graphics SDK and GPU HAL for MCU platforms. Design, implement, and maintain graphics APIs, GPU and display HALs; develop example apps and tests; perform pre-silicon FPGA verification, post-silicon bring-up, system validation, and hands-on debugging; support DV, field engineers, and customers.

Lead and scale the physical implementation organization for ultra-low-power MCU products. Define strategy, build and mentor teams, oversee full-chip and block-level physical design (floorplanning, power planning, CTS, P&R, timing closure, DRC/LVS, EM/IR signoff), collaborate cross-functionally, manage schedules and tape-out readiness, and ensure first-silicon success and manufacturability.

Lead timing methodology and closure for block and SoC levels in modern FinFET/multi-patterning processes. Define flows, constraints, signoff correlation, timing margining, glitch noise analysis, and collaborate with RTL, PnR, DFT, and post-silicon teams to achieve timing convergence and best-in-class PPA.

Lead end-to-end memory deployments: define memory roadmap, evaluate and simulate memory architectures (SRAM/DRAM/HBM/RRAM/MRAM), lead characterization, work with architects, circuit and process teams, and third-party vendors to ensure energy-efficient, high-yield memory integration.