Ambiq

HQ
Austin
Total Offices: 4
220 Total Employees
185 Product + Tech Employees
Year Founded: 2010
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Ambiq Offices

Ambiq is headquartered in Austin and has 4 office locations.

OnSite Workplace

Employees work from physical offices.

Building silicon and embedded AI systems requires tight collaboration across firmware, hardware, validation, and architecture teams. We believe the hardest engineering problems are solved through direct, daily collaboration.

Typical time on-site: 5 days a week

U.S. Office Locations

HQ Austin

Global Office Locations

China Singapore Jiangsu
HQ

Austin

6500 River Place Blvd, Building 7, Suite 200, Austin, Texas, United States, 78730 1119

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China

China

China

Singapore

Singapore

Aperia Tower 2, 10 Kallang Avenue, #14-10 to 13, Singapore, Singapore, 339510

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Jiangsu

Taiwan

Taiwan, Province of China

Jobs At This Office

Recently posted jobs

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Ambiq

Field Application Engineer - West Coast

2 Days AgoSaved
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In-Office or Remote
Austin, Texas, USA
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Hardware • Internet of Things • Software • Wearables • Semiconductor
The Field Application Engineer will support global customers in design-in activities, develop product solutions, optimize power consumption, and assist with customer HW/SW development.
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Ambiq

Field Application Engineer - Central US

2 Days AgoSaved
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In-Office or Remote
Austin, Texas, USA
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Hardware • Internet of Things • Software • Wearables • Semiconductor
The Field Application Engineer supports global customers by aiding in the design-in process of Ambiq's low-power semiconductor solutions, optimizing energy efficiency, and developing hardware and software for embedded systems. Responsibilities include design reviews, customer collaboration, debugging, and presenting complex technical topics.
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Ambiq

Sr. Staff Engineer - DFT

2 Days AgoSaved
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In-Office
Austin, TX, USA
Easy Apply
Hardware • Internet of Things • Software • Wearables • Semiconductor
Lead DFT strategy for ultra-low-power SoCs: design and implement scan, boundary scan, MBIST, ATPG and low-power DFT architectures; generate and analyze structural test vectors; run pre/post-layout simulations; collaborate with design, verification, and test teams to optimize coverage, test time, cost, and bring-up test vectors on silicon.
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