Sr Staff Mask Design Engineer

Posted 9 Hours Ago
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Bengaluru, Bengaluru Urban, Karnataka, IND
Hybrid
Senior level
3D Printing
The Role
Lead and deliver high-quality, manufacturable analog and mixed-signal IC layouts (IP/block/SoC). Drive floorplanning, power distribution, application of advanced layout techniques, physical verification (DRC/LVS/DFM/PEX), collaborate with cross-functional teams, support first-silicon debug, and contribute to methodology, training, and team leadership.
Summary Generated by Built In
Company Description

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

Business Unit Description

The Power Product Group (PWR) is responsible for delivering power management solutions across automotive, computing, consumer, and industrial markets. Within PWR, the Automotive System Power (ASP) division focuses on automotive power management and system power solutions, supporting advanced vehicle architectures and safety‑critical applications.

ASP brings together expertise in automotive system power, system attach PMICs, and automotive battery management ICs, delivering highly reliable solutions that meet stringent automotive quality, functional safety, and long‑term reliability requirements. The division works closely with cross‑functional teams across design, layout, technology, test, and manufacturing to deliver robust SoC and IP solutions for automotive customers worldwide.

As part of the global PWR organization, ASP operates in a multisite, multicultural environment, emphasizing strong collaboration, technical excellence, and alignment across product lines to support Renesas’ automotive growth strategy.

Job Description

We are looking for an experienced Sr Staff Mask Design Engineer to join a highly skilled layout organization working on Analog and Mixed‑Signal ICs for Automotive applications.
The role involves defining, developing, and delivering high‑quality, manufacturable IC layouts using industry‑standard technologies and tools.

The successful candidate will contribute at block and top level, support or lead layout activities, collaborate closely with design and cross‑functional teams, and ensure robust physical implementation that meets performance, reliability, and quality requirements.

Job Purpose

The purpose of this role is to deliver robust, high‑quality physical layouts for complex analog and mixed‑signal ICs, ensuring manufacturability, reliability, and on‑time delivery, while contributing to layout methodology, team capability, and continuous improvement.

Key Responsibilities

As a Sr Staff Mask Design Engineer, you will be responsible for:

  • Implementing physical layouts for Automotive Business Line products at IP, block, and/or SoC level
  • Driving and delivering floorplanning activities for blocks and top‑level designs
  • Participating in power supply strategy definition and signal distribution between blocks
  • Delivering analog and mixed‑signal layout blocks and contributing to top‑level floorplan strategy
  • Applying state‑of‑the‑art layout techniques for device matching, parasitic reduction, ESD protection, latch‑up prevention, and yield optimization
  • Executing and signing off physical verification flows, including DRC, LVS, ERC, DFM, and parasitic extraction (PEX)
  • Working according to Analog‑on‑Top and Mixed‑Signal‑on‑Top layout methodologies
  • Attending relevant project and design reviews, reporting progress, risks, and schedule impacts
  • Collaborating closely with design, verification, CAD, and technology teams to minimize rework and resolve physical implementation issues
  • Identifying root causes and proposing solutions for issues observed during first silicon or prototype evaluation
  • Contributing to design‑for‑quality, ensuring layouts are verified, validated, and suitable for long‑term reliability and zero‑defect goals
  • Supporting or leading layout team activities, including task planning, execution, and knowledge sharing
  • Participating in and contributing to training activities, technical documentation, and layout guidelines
  • Taking a proactive role in personal development, continuous learning, and methodology improvement

Qualifications

Education & Experience

  • Bachelor’s or Master’s degree in Electrical, Electronics, or Microelectronics Engineering
  • 8+ years of experience in Analog and Mixed‑Signal IC layout design
  • Proven experience delivering complex layouts at IP, block, and/or SoC level
  • Experience in automotive or safety‑critical semiconductor products is highly desirable

Technical Skills

  • Strong expertise in analog layout techniques, including:
    • Floorplanning and top‑level integration
    • Device matching and symmetry
    • Parasitic management
    • Latch‑up prevention and ESD protection
  • Solid understanding of electronics, semiconductor physics, and fabrication processes
  • Hands‑on expertise with layout and verification tools, including:
    • Cadence Virtuoso / Virtuoso XL (OA, PVS)
    • Mentor Graphics Calibre (DRC, LVS, PEX, DFM)
    • R3D and related parasitic extraction tools
  • Experience with advanced CMOS BCD technologies
  • Experience using Mixed‑Signal‑on‑Top (MSoT) flows
  • Ability to define and execute advanced floorplan strategies

Soft Skills & Ways of Working

  • Strong team player, self‑motivated, and results‑oriented
  • Ability to work independently and collaboratively in a multisite, multicultural environment
  • Excellent verbal and written English communication skills
  • Clear, concise communication and presentation skills
  • Ability to propose innovative and pragmatic solutions
  • Strong focus on quality, reliability, and on‑time delivery
  • Willingness to undertake occasional international travel if required
  • Comfortable collaborating with cross‑functional teams including design, test, program management, and quality

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Skills Required

  • Bachelor's or Master's degree in Electrical, Electronics, or Microelectronics Engineering
  • 8+ years of experience in Analog and Mixed-Signal IC layout design
  • Proven experience delivering complex layouts at IP, block, and/or SoC level
  • Experience in automotive or safety-critical semiconductor products
  • Expertise in analog layout techniques: floorplanning, device matching, parasitic management, latch-up prevention, ESD protection
  • Solid understanding of electronics, semiconductor physics, and fabrication processes
  • Hands-on expertise with layout and verification tools (Cadence Virtuoso/Virtuoso XL, OA, PVS; Mentor Graphics Calibre (DRC/LVS/PEX/DFM); R3D and parasitic extraction tools)
  • Experience with advanced CMOS BCD technologies
  • Experience using Mixed-Signal-on-Top (MSoT) flows and defining/executing advanced floorplan strategies
  • Excellent verbal and written English communication and collaboration skills; ability to work in multisite, multicultural teams
  • Willingness to undertake occasional international travel

Renesas Electronics Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Renesas Electronics and has not been reviewed or approved by Renesas Electronics.

  • Fair & Transparent Compensation Feedback suggests pay is generally fair-to-good across many roles, with base pay aligned to prevailing market levels in multiple U.S. locations. Engineering and leadership tracks can be competitive on total compensation, reinforcing a sense that pay can meet market expectations in key job families.
  • Healthcare Strength Feedback suggests core medical, dental, and vision coverage is solid and well-regarded by employees. Day-one eligibility in U.S. roles is described, supporting confidence in access and continuity of care.
  • Leave & Time Off Breadth Feedback suggests PTO, paid holidays, sick time, and parental leave provide a comprehensive time-off framework. Company initiatives like Renesas Day and meeting-light Focus Fridays further support time away and balance.

Renesas Electronics Insights

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The Company
HQ: Tokyo
10,040 Employees

What We Do

We're the world's leading semiconductor manufacturer. Our mission is to make our lives easier and a world that's safer, healthier, greener, and smarter.

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