Sr Principal Design Engineer

Posted Yesterday
Be an Early Applicant
Cary, NC, USA
In-Office
154K-286K Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Leads mixed-signal physical IP development for high-speed serial links. Designs and verifies circuits from architectural specifications, develops and executes post-silicon test plans, collaborates with digital teams on functional and performance closure, and contributes to validation, testing, and project leadership.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We offer amazing opportunities to grow, no matter where you are in your career.

This is an opportunity to join a dynamic team of experienced engineers developing physical IP for industry-standard high-speed serial-links.


The successful candidate will ideally be a highly-motivated self-starter who can work independently to complete assigned tasks and contribute to project leadership. The candidate will contribute to all mixed-signal design, verification, and testing aspects. This includes circuit design and development from a high-level architectural specification, post-silicon test plan development and execution, and collaboration with the digital team to achieve functional and performance closure.


Candidate must have a thorough understanding of the following: 

  • Mixed-signal circuit design fundamentals
  • Mixed-signal circuit design and verification flows
  • Cadence analog design environment
  • Basic signal processing concepts

Familiarity with the following items is a plus:

  • Serial link design techniques
  • Data converter (ADCs and/or DACs) and/or clock synthesis and recovery (PLLs, DLLs, CDRs) techniques
  • MATLAB or C to facilitate architecture development
  • Hardware description languages such as SystemVerilog or VerilogA for functional model development
  • Scripting languages such as Perl or Python for automation
  • Silicon validation testing knowledge and experience

Other requirements:

  • Excellent verbal and written communication skills
  • Ph.D. EE degree with 5+ years or MS EE. degree with 7+ years of mixed signal design industry experience in advanced process technologies

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

Be proud and passionate about the work you do. Together, our One Cadence -- One Team culture drives our success. 

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Ph.D. in Electrical Engineering with 5+ years of mixed-signal design industry experience
  • Master of Science in Electrical Engineering with 7+ years of mixed-signal design industry experience
  • Experience with advanced process technologies
  • Thorough understanding of mixed-signal circuit design fundamentals
  • Experience with mixed-signal circuit design and verification flows
  • Experience with Cadence Analog Design Environment
  • Basic signal processing knowledge
  • Excellent verbal and written communication skills
  • Familiarity with serial link design techniques
  • Familiarity with ADC, DAC, PLL, DLL, or CDR techniques
  • Familiarity with MATLAB or C
  • Familiarity with SystemVerilog or Verilog-A
  • Familiarity with Perl or Python scripting
  • Silicon validation testing knowledge and experience

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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