Senior Staff Engineer, DFT

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Switch DFX team in Data center Engineering (DCE) is responsible for overall DFT solution implemented in all Marvell Switch products. The team owns DFX Strategy, DFX Architecture, DFX IP's and all aspects of SoC MBIST and ATPG definition, implementation, validation pre and post-Si.

What You Can Expect

• Work on all aspects of DFT for high-performance switch products, including architecture, test strategy, flow, implementation, verification, and post-silicon bring-up
• Collaborate with DFT team members for feature implementation, integration, and verification at SoC level
• Interface with cross-functional teams including Logic Design, Physical Design, STA, and ATE for seamless DFT execution
• Contribute to development and refinement of DFT methodologies and flows
• Ensure high-quality DFT deliverables for successful tapeout and silicon validation

What We're Looking For

• Bachelor’s degree in Electrical/Electronics Engineering with 7+ years of DFT experience or Master’s degree with 3–5 years of experience
• Strong knowledge of SCAN, ATPG, JTAG, and MBIST
• Experience in gate-level simulations including no-timing and SDF-based for DFT modes
• Hands-on with DFT test structures, IP integration, ATPG fault models, test point insertion, and coverage improvement
• Proven expertise in scan insertion at block and chip top levels
• Good understanding of test mode timing constraints
• Ability to resolve DFT issues across design, synthesis, physical design, and STA teams
• Proficient in industry-standard DFT tools (Synopsys/Mentor preferred)
• Solid knowledge of JTAG standards IEEE 1149.1/1149.6
• Experience in post-silicon ramp-up and ATE debug
• Hands-on with MBIST generation, insertion, and verification at RTL and netlist level
• Proficient in Perl and Tcl scripting
• Strong communication skills and ability to work with global teams
• High ownership and accountability for tapeout and post-silicon success

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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