The Senior Staff Applications Engineer will support PCIe products, resolve customer issues, and collaborate with engineering and marketing teams, requiring strong DSP and circuit knowledge.

As a Staff Engineer in Physical Design, you'll work on physical designs and methodologies for advanced chips, focusing on PnR, timing analysis, and verification processes.

As an Analog Layout Staff Engineer, you will collaborate on the design and verification of high-speed analog circuits, working with global teams and participating in all aspects of the project lifecycle.

The Principal Package Design Engineer will lead advanced package design, improve workflows, and collaborate cross-functionally to innovate and validate new PCB substrates for high-performance computing.

Design Verification Engineer responsible for developing verification plans, creating testbenches, debugging failures, and mentoring junior engineers in complex digital design verification.

As a Senior Principal Analog Design Engineer, you'll lead SerDes development for advanced nodes, design analog circuits, and collaborate on architecture development and testing.

As Senior Director, lead the development of semiconductor design strategies, manage a multi-disciplinary team, oversee productization, and drive innovation in data processing silicon.

Lead product management efforts for Layer 1 software solutions, collaborating across teams to define strategies, build roadmaps, and represent Marvell in industry forums.

Responsible for New Product Introduction and silicon bring-up, collaborating with cross-functional teams to analyze yield and drive test improvements.

Lead DV execution for SoC products, improve DV processes, collaborate with cross-functional teams, and debug simulation failures. Requires extensive experience in IP and SoC verification.

As a Senior Principal Analog Design Engineer, you will lead design efforts for high-speed analog circuits, collaborating with teams to deliver innovative IP solutions.

Design and validate high-speed broadband ICs and transimpedance amplifiers for optical communication, providing technical leadership and guiding teams in implementation.

The role involves performing Static Timing Analysis, ensuring design integration, providing technical guidance, and automating tasks using scripts. Collaboration with teams across disciplines is key.

Lead the cybersecurity team to ensure compliance with regulations, conduct risk assessments, and develop security policies while managing audits and incident responses.

The role involves DFT solutions for switch products, collaborating with teams for implementation and validation, and ensuring quality DFT deliverables.

Design, simulate, and analyze high-speed optical communication systems. Develop optical models, optimize performance, and perform signal integrity analysis for next-gen architectures.

The Senior Principal Switch Architect will lead the architecture of data center switch ASICs, defining features and collaborating on implementation. Requires extensive experience in ASIC design and networking protocols.

The Senior Analog Layout Engineer designs microelectronic layers using CAD tools, collaborates with engineers to refine designs, and presents project updates.

Design highly sophisticated CMOS transceiver/SERDES products, leading architectural investigations and circuit design, ensuring performance targets are met and validating designs through testing.

As a Senior Engineer in Analog Layout, you will design microelectronic layers, run simulations, and collaborate with global teams to refine and debug designs.