Search the 154 jobs at Marvell Technology

The Staff Supply Chain Analyst at Marvell will analyze supply chain data to identify inefficiencies and trends, design dashboards to visualize metrics, and collaborate with various departments to implement data-driven strategies to enhance operational efficiency and performance.

As a Design Engineering Junior at Marvell, you will work on developing high-speed PAM/Coherent DSPs and PHY designs. Your responsibilities include performing digital design tasks, coding in scripting languages, optimizing DSP architectures, and collaborating with cross-functional teams in a dynamic, international environment.

As a Staff Engineer, you will develop custom circuits for various technology nodes, understanding customer needs and overseeing the design process from inception to delivery. Responsibilities include designing memory and security IPs, custom analog circuits, validating hardware results, conducting failure analysis, and documenting development activities.

This role involves developing and maintaining a verification environment in UVM, defining verification test plans, verifying designs using directed and constrained random parameters, and driving verification coverage targets. The engineer will also be responsible for debugging test failures and collaborating with designers.

The Principal RTL Design Engineer at Marvell will lead a significant part of Switch design, from micro-architecture to tape-out. Responsibilities include coding micro-architected designs, integrating third-party IP, collaborating with various teams for DFT and DV, and supporting physical design for timing analysis.

The Principal Engineer will focus on verifying complex System on Chips (SoCs) and multi-SoC systems, developing verification architectures, writing test plans, developing tests, debugging failures, and maintaining verification tools for multicore SoCs.

The Principal Analog Mixed-Signal Design Engineer will be responsible for the design and validation of RF and analog circuits for high-speed broadband ICs, focusing on Transimpedance Amplifiers and optical interface chips. The role involves active circuit design, technical leadership, and collaboration on post-silicon validation and transition to mass production.

Design and implement advanced CMOS transceiver/SERDES products, focusing on architectural investigations and verification for various analog circuits. Responsibilities include layout activities, lab testing, and support for design integration with digital teams.

The Principal Digital Design Engineer will assist in chip design and verification for optical Ethernet transceiver ASICs, focusing on high-speed data path RTL implementation, ASIC specification, and team mentorship. Responsibilities include managing entire design cycles, post-silicon debug, and collaborating with backend teams to ensure product functionality.

As a Principal Engineer on Marvell's SW team, you will lead and mentor developers in embedded firmware development for optical communication products. Responsibilities include architectural design, project management, debugging hardware/software issues, and collaborating with cross-functional teams to ensure product success from development to production.

The Staff Engineer in Test Engineering at Marvell will develop ATE test programs and hardware, manage production testing, support new product qualifications, and work collaboratively with design teams to ensure optimal performance and cost efficiency in testing processes.

As a Senior Principal Design Verification Engineer at Marvell, you will design and verify SoCs for AI/ML and network processing. Responsibilities include developing verification environments, writing detailed test plans, debugging failures, and architecting tools for multi-core SoCs.

The Trade Compliance Manager is responsible for ensuring compliance with export and import regulations at Marvell's Vietnam location. This role involves liaising between business functions and the Global Trade Compliance team, overseeing import/export transactions, and developing compliance processes, while monitoring trade compliance risks and providing necessary training and support to stakeholders.

The Digital IC Design Staff Engineer will engage in designing and verifying Automotive Ethernet and Ethernet PHY front-ends, collaborating with cross-functional teams and writing technical specifications. The role requires extensive knowledge of semiconductor ASIC design methodologies, Verilog, SystemVerilog, and UVM, along with strong analytical and problem-solving skills.

Design highly sophisticated CMOS transceiver/SERDES products, focusing on architectural investigations and implementation of various circuits including PLL, DLL, and ADC. Responsible for design verification using SPICE and MATLAB, as well as working with test engineers for characterization and debugging of designs.

The Senior Staff Finance Manager will lead the financial planning and analysis for the Connectivity Business Unit, manage and mentor a finance team, develop financial models, and provide strategic financial analysis to senior management while ensuring compliance with GAAP and driving process improvements.

The Senior Staff Engineer will develop high-speed Analog SerDes in advanced technology nodes, collaborate with design teams, provide layout instructions, and support prototypes through characterization and validation with a strong focus on low power and high-speed design techniques.

As a Signal Integrity Principal Engineer, you will design advanced structures for high-speed interfaces, develop solutions for signal integrity challenges, validate designs through high-speed measurements, and collaborate with teams to integrate these solutions.

The Emulation Engineer will modify RTL to create emulation-friendly wrappers and enhance compile/run times using scripts. They will work on AI-enabling server chipsets and be responsible for the transition of RTL into emulation platforms.

As a Cyber Threat Hunting and Intelligence Analyst at Marvell, you will identify and respond to cyber threats, develop detection logic and response playbooks, produce threat reports, and collaborate with the SOC and CSIRT teams to enhance threat detection and response capabilities.