Search the 143 jobs at Marvell Technology

The Staff Engineer in Analog Layout will design and optimize analog mixed-signal layouts, work with circuit designers to meet specifications, and ensure that layouts comply with design rules. Responsibilities include floor planning, custom layout, verification, and maintaining documentation of methodologies and decisions.

The Analog Mixed Signal Design Engineer will work with a team on architectural investigations and implementation of circuits like PLL, DLL, ADC, and regulators. Responsibilities include design verification using tools like SPICE and Spectre while collaborating with layout and verification teams, and managing the delivery of analog IP from concept to production.

The Principal Analog Mixed Signal Design Engineer will work on designing high-speed and optical transceivers, focusing on circuits like PLLs, DLLs, ADCs, and amplifiers. Responsibilities include ensuring performance targets, design verification using tools like SPICE and MATLAB, and managing the delivery of analog IP from concept to production, collaborating with layout and verification teams.

The role involves architectural investigations and implementation of circuits like PLL, DLL, ADC, and amplifiers, ensuring performance targets are met. The candidate will design and verify analog IP and interface with various teams to bring designs from concept to production.

The Principal Engineer, Reliability will oversee new product qualification of semiconductor products, conduct reliability stress testing, and collaborate with internal and external partners on project execution. Responsibilities include data analysis, managing multiple qualifications, and developing monitoring programs to enhance product reliability.

The Analog Design Engineer, Principal will analyze design specifications, create and supervise transistor-level analog designs for multi-GHz applications, ensure post-layout verification, model and validate analog performance, and mentor junior designers while collaborating with cross-functional teams.

The Senior Principal Analog Mixed Signal Design Engineer is responsible for designing sophisticated CMOS transceiver IPs and other crucial components. Key tasks include architectural investigations for circuits, design verification using standard tools, and managing delivery of analog IP from concept to production. Collaboration with layout, verification, and application teams is essential.

Lead a team of layout designers in analog layout design, manage schedules and risks, perform hands-on macro-level layouts and coordinate with various teams to ensure project timelines are met.

The Staff Design Verification Engineer is responsible for the verification and evaluation of digital circuits in high-speed data communication ICs, developing verification plans, test environments, and executing test cases, particularly focusing on PCIE, Ethernet, and Serdes PHY functionalities using UVM and SystemVerilog.

The Senior Staff Engineer in DFT at Marvell will be responsible for DFT architecture, implementation, verification, and post Si bring-up for Switch products. The role involves working on SCAN, ATPG, JTAG, and MBIST, collaborating with various teams, and addressing DFT issues in design and synthesis.

The Senior Staff Analog Layout Engineer will oversee chip layout, manage project schedules, collaborate across teams, implement guidelines, contribute to team development, and stay updated on technological advancements. A deep understanding of layout methodology and advanced processes is essential, with experience in common EDA tools and languages.

As an Analog IC Design Staff Engineer at Marvell, you'll work on high-speed and high-performance SerDes development, participating in architecture development with interdisciplinary teams, guiding layout engineers, and collaborating on IP characterization. You'll also provide support for SOC and customer debugging.

As a Staff Engineer in Analog Layout, you'll collaborate with global teams to run simulations and verifications using Cadence Virtuoso. You'll oversee the design process from layout to verification, ensuring designs meet specifications and participating as a mentor in project meetings.

The role involves leading the design of Analog IC products, specifically CMOS transceiver/SERDES/PLL circuits. Responsibilities include architectural investigations, implementation, and design verification while managing delivery with a team of design engineers.

As a Senior Staff DFT Engineer at Marvell, you will implement DFT/Test on complex IP and SoCs for custom ASIC/SoC designs. You'll lead DFT/Test efforts, utilize DFT/Test architecture solutions, and develop methodologies for DFT/Test domains, leveraging your expertise in digital circuit design and verification using various EDA tools and scripting languages.

The Principal Physical Design Engineer will lead chip-level Place and Route activities ensuring high-performance designs. This role involves hands-on design work, technical leadership, tool optimization, and collaboration with various teams while mentoring junior engineers in the semiconductor field.

As a Senior Staff Engineer in Analog IC Design at Marvell, you will focus on high-speed and high-performance SerDes development. Responsibilities include designing mixed signal circuits, working with layout engineers, and collaborating with DSP and digital design teams on architecture development, characterization, and validation.

The Senior Staff Analog IC Design Engineer is responsible for designing complex CMOS transceiver/SERDES products, conducting detailed circuit design and verification using industry-standard tools, overseeing layout activities, and collaborating with cross-functional teams to ensure successful design integration and performance validation.

The Staff Engineer in Design Verification will analyze specifications to create test plans, develop UVM components, write test cases, run simulations, and debug issues. The role involves improving coverage results and proposing fixes through GLN/SDF simulation.

The role involves designing and verifying circuits such as PLL, DLL, ADC, and amplifiers, focusing on high-speed transceivers for communication infrastructure. The successful candidate will collaborate with layout and verification teams and manage the delivery of analog IP from concept to production.