Jobs at Marvell Technology

Lead development and automation of physical verification CAD/EDA flows (DRC/LVS) and runsets using Calibre and ICV. Integrate and maintain EDA toolchains, support tape-outs and foundry interfaces, debug verification issues, create validation tests and documentation, and provide technical guidance and training across design teams.

Lead micro-architecture and RTL development and HW/SW co-design for SoC and IP (memory controllers, PCIe, CXL). Collaborate with architects and verification teams to deliver high-performance, timing-critical designs through front-end flow, timing closure, and power optimization.

Lead verification of complex CPU subsystems and SoCs: create testbenches, test and coverage plans, develop verification environments, run constrained-random tests, collect functional coverage, debug with tools, mentor engineers, and own subsystem/IP verification flows to meet criteria.

Lead micro-architecture and RTL development for SoC component IP (memory controllers, PCIe/CXL). Perform HW/SW co-design, timing closure, power optimization, RTL quality checks, and collaborate with architects and verification teams to deliver production-quality, timing-critical designs.

Lead and execute SoC and CPU subsystem design verification: develop testbench architecture, test and coverage plans, implement constrained-random tests and functional coverage, debug with Verdi/Incisive, mentor verification engineers, and own verification flows and methodologies to meet IP/subsystem and full-chip verification criteria.

Lead board-level architecture, schematic/BOM creation, PCB layout oversight, and manufacturing for photonic/data-center platforms. Drive system bring-up, debugging, validation, cross-functional coordination, vendor management, and project execution to deliver server and rack-level solutions.

The Staff Engineer will design and verify digital circuits for high-speed data communication ICs, including developing verification plans, collaborating with cross-functional teams, and performing test integration.

Responsible for post-RTL design flow and timing closure for SerDes IPs, collaborating with teams to deliver competitive solutions.

The Analog Layout Senior Engineer role involves developing high-speed SerDes IPs, designing complex analog/mixed-signal layouts, ensuring verification closure, mentoring junior engineers, and developing automation scripts.

Lead the development of high-speed SerDes IPs, design complex analog layouts, collaborate with circuit designers, ensure physical verification, and mentor junior engineers.

As a Test Hardware Engineer, you'll test semiconductor chips, work with design teams to ensure testability, and develop testing strategies as needed.

The Director will define application roadmaps for Legal, Compliance, and Facilities technology, lead implementation of key applications, and manage cross-functional project teams while ensuring stakeholder engagement and operational excellence.

The Senior Principal Engineer will develop and implement methodologies for design automation, integrate AI in design flows, manage tools and infrastructure, and collaborate with cross-functional teams to enhance workflows and productivity.

The Principal Foundry Tapeout Engineer will oversee tapeout execution, coordinate between cross-functional teams, and manage logistics for semiconductor manufacturing. Responsibilities include database management, tapeout automation, and cost evaluation alongside project management in a dynamic environment.

The IP Program Manager manages IP development and delivery for Marvell’s products, collaborating across teams to meet specifications and support engineering management processes.

As a Senior Staff Engineer, you will enhance digital design flows for high-performance SerDes IP, optimize automation frameworks, collaborate on IP development, and support EDA integration, all while leveraging AI/ML techniques in a Linux environment.

Define and improve design verification processes, collaborate on test plans, debug simulation failures, and architect testbenches using UVM and C. Verify design correctness for PCIe/CXL subsystems with 18+ years of experience.

Lead the design verification team for ASIC development, ensuring high-quality product delivery through effective collaboration and innovative methodologies.

The Staff Hardware Engineer will design, develop, and test electrical hardware for optical modules and AI platforms, collaborating on specifications, performing testing, and supporting production.

Lead development of ATE test solutions for characterization, wafer sort, and production on Advantest 93K/Teradyne UltraFLEX. Design high-speed test hardware, define test methodologies, translate simulation patterns to ATE programs, optimize test flows, and collaborate cross-functionally to improve yield and release production test programs.