Jobs at Marvell Technology

The Staff DFT Engineer role involves developing and implementing efficient design for test strategies for semiconductor solutions, directly impacting data infrastructure technologies.

The role involves design verification of CPU sub-systems, mentoring engineers, and managing verification flows for complex ASIC projects.

As a Senior Staff Engineer in Test Engineering, you'll develop test programs for semiconductor chips, ensuring quality and performance while collaborating with design teams and optimizing testing methodologies.

As a Senior Staff Engineer, you will architect and model wireline communication systems, develop DSP techniques, and lead modeling and verification efforts.

The Staff Analog Layout Engineer will design high-performance analog circuits, manage project schedules, collaborate with cross-functional teams, and ensure adherence to design guidelines.

The Inside Sales Representative at Marvell focuses on sales management by developing strategies, managing relationships, analyzing data, and providing actionable insights to achieve revenue goals.

As a Senior Principal Product Engineer, you will lead NPI activities for semiconductor products, drive product engineering execution, optimize methodologies, and foster collaboration across global teams to ensure product success.

Lead SoC microarchitecture and RTL design for high-performance custom SoCs: implement Verilog/SystemVerilog RTL, integrate complex IP and interfaces, collaborate with verification and physical design to close timing/PPA, run lint/CDC checks, support synthesis, formal and gate-level verification, and improve integration workflows and methodology.

Lead micro-architecture and RTL development for complex SoC blocks. Implement synthesizable Verilog/SystemVerilog, ensure correctness via lint/CDC/RDC, collaborate with verification, synthesis/STA, physical design and firmware teams, debug timing/power/integration issues, mentor engineers, and drive tape-out readiness.

Lead end-to-end product programs from customer quote through production ramp, sustaining manufacturing, and end‑of‑life. Own scope, schedule, cost, supply, risks, and customer commitments while coordinating cross‑functional and external manufacturing partners. Drive quotes, capacity assessment, program launches, KPI tracking, change management, and EOL strategies. Maintain dashboards and present status to senior leadership and customers.

Serve as on-site HR liaison for Burlington, Rochester, and Minnetonka sites. Support site leaders, guide managers on performance and policy, foster culture alignment, lead HR communications, assist with enrollments/training, support investigations, act as primary I-9 agent, and travel quarterly to Minnesota sites and annually to headquarters.

Design and verify full‑custom analog layouts for next‑generation high‑speed SerDes IPs in advanced FinFET nodes. Perform RC extraction, EMIR/ESD/antenna layout solutions, physical verification (DRC/LVS/DFM) using Cadence Virtuoso, collaborate with global teams, and help automate layout flows.

Manage Marvell's global mobility, U.S. immigration, and relocation programs end-to-end. Serve as SME on visa/work authorization strategies, track case timelines, review filings and invoices, manage vendor performance, support RFEs, audits, escalations, and maintain process documentation and metrics.

The role involves physical design and methodology for advanced processor chips. Responsibilities include collaborating with design teams, implementation, mentoring, and scripting for automation.

The Design Verification Engineer will develop functional verification environments, write test plans, debug failures, and mentor junior engineers while ensuring design specifications are met.

The Principal AMS Verification Engineer will design and verify high-speed analog and mixed-signal circuits for photonic transceivers, develop verification testbenches, write test cases, and collaborate with multidisciplinary teams to enhance system performance and documentation.

The role involves pre/post-sales support for customer designs, validation, debugging, and training related to high-speed optical modules and communication hardware.

Lead physical design efforts for next-gen high-performance processors, manage teams, mentor engineers, ensure timely tapeouts and enhance design methodologies.

The Director leads hardware engineering focusing on high-speed board design and signal integrity, overseeing design, validation, and team leadership.

The Senior Staff Analog Layout SRAM Engineer will lead SRAM memory layout development, collaborate with circuit designers, ensure verification closures, mentor junior engineers, and develop automation scripts to enhance productivity.