Lead the architecture and execution of next-generation data center switch products, collaborating across teams to define features and ensure performance validation.

The Principal Applications Engineer will drive the integration of SerDes IP across platforms, providing technical support, optimizing designs, solving problems, and collaborating with cross-functional teams.

Lead DFT architecture and implementation for custom ASICs, advise Vietnam and global teams, improve DFT methodology using latest EDA (Tessent), coordinate cross-functional execution, and support silicon bring-up to mass production readiness.

The Principal Customer Quality Engineer leads quality engagements for key accounts, performs failure analysis, advocates for quality compliance, manages cross-functional teams, and provides strategic quality reports.

The role involves designing and validating high-performance analog circuits, leading TIA projects, and collaborating for post-silicon validation in high-speed data communication applications.

Design and layout very large-scale silicon photonic ICs (PICs) from floor-planning to back-end verification. Collaborate with analog, digital and packaging teams to meet opto-electronic, SI and PI requirements. Optimize and extend layout automation and verification flows using scripting and EDA tools to deliver production-ready PICs.

As an Analog Engineer Intern, you will work on high-speed analog and digital circuit design, behavioral modeling, and calibration algorithms to support data conversion and connectivity solutions.

The Principal Digital IC Design Engineer will develop RTL, collaborate on design projects, and mentor engineers in secure computing solutions.

The role involves building and maintaining dashboards for engineering insights, integrating data, defining KPIs, and improving data quality across teams in a semiconductor context.

As an Analog IC Design Engineer Intern, you'll design high-performance analog circuits, learn CAD tools, and collaborate on advanced technology for AI and cloud applications.

The Global Account Manager leads Marvell's cloud sales strategy for semiconductor solutions, fostering customer relationships, driving sales, and ensuring successful deal closures.

The Principal/Staff Engineer in DFT Engineering will own design flow control, enhance DFT flows, collaborate with teams, and drive automation for efficient design processes.

Develop and maintain automated design flows for RTL validation, enhance CAD efficiency with AI tools, and interface with EDA vendors.

Design and verify CMOS transceiver/SERDES products, implementing circuits like PLLs and ADCs, using tools like Spectre and MATLAB.

Drive DFT innovation and control design flows for next-gen compute and storage silicon, enhancing automation and supporting engineering teams.

The Senior Staff Engineer will develop high-speed and high-performance Analog SerDes, collaborate with design teams, optimize layouts, and support IP characterization.

The Director, Assistant General Counsel will provide legal support to Marvell's operations in India, focusing on compliance, regulation, and commercial issues while guiding government relations. Responsibilities include advising management, drafting legal documents, negotiating disputes, and managing litigation.

Lead the SOC design team, manage high-quality SOC designs, integrate IPs, and ensure successful product execution through collaboration and technical leadership.

Design and execute DFT and ATPG flows for custom silicon: insert and verify scan, MBIST, and IP test; generate and simulate test patterns; analyze coverage; support manufacturing test bring-up and debug; collaborate on flow improvements.

Design and verify full-custom analog/mixed-signal layouts for high-speed SerDes and foundational IPs using advanced FinFET nodes. Perform RC extraction, physical verification (DRC/LVS/DFM), EMIR/ESD/antenna mitigation, collaborate with global teams, and support automation/programming for layout flows.