Jobs at Marvell Technology

Leads DFT architecture, implementation, validation, timing analysis, pattern generation, and post-silicon bring-up for complex mixed-signal SoCs. Defines and improves DFT methodologies and tools across multiple chip generations, while mentoring and guiding a team of DFT engineers. Requires deep experience with SCAN, MBIST, IP-DFT, STA, DFX, ASIC design flows, and industry-standard Cadence, Mentor, and Synopsys tools.

Staff DFT Engineer responsible for implementing scan, compression, OCC, wrappers, and MBIST; running ATPG, DFT DRC, simulations, and coverage analysis; supporting timing closure and silicon bring-up; debugging ATE patterns; and automating DFT flows with scripts. The role requires collaboration with physical design and STA teams on advanced ASIC programs.

Define and implement DFT architecture for complex SoCs, including hierarchical DFT, scan, compression, ATPG, MBIST, JTAG, and at-speed testing. Lead DFT sign-off, timing and equivalence checks, silicon debug, failure diagnosis, yield learning, and handoff to physical design and ATE teams. Mentor engineers, coordinate cross-functionally, and improve DFT methodology and automation for advanced-node optical DSP products.

Leads complex semiconductor platform programs from concept through production readiness. Coordinates board, switching, optics, silicon, firmware, software, validation, manufacturing, supply chain, customers, and executive stakeholders. Owns integrated plans, technical integration, risk mitigation, validation, issue resolution, customer commitments, and production transition for hyperscale cloud and networking solutions. Improves program execution practices while balancing schedule, scope, quality, cost, resources, and platform objectives.

Owns technical development programs end to end, including design, cohort planning, training, mentoring, workshops, events, communications, evaluation, and continuous improvement. Partners with engineering teams and senior stakeholders to assess development needs, define objectives and metrics, manage milestones and risks, coordinate global delivery, and apply AI and analytics. Maintains program infrastructure, budgets, vendors, websites, and toolkits while supporting technical conferences and other development initiatives.

Leads the global strategy, governance, roadmap, budget, and delivery of technical training, career development, and technical leadership programs. Partners with senior engineering leaders, conducts skills and workforce analyses, designs scalable programs, and measures outcomes such as retention, productivity, and technical bench strength. Guides regional program managers, mentors team members, evaluates emerging technologies, and aligns technical development initiatives with engineering priorities and product roadmaps.

Leads semiconductor IP development and delivery from conception through mass production release. Manages dependencies, deliverables, specifications, milestones, risks, and cross-functional engineering teams across analog, logic, DFT, layout, timing, validation, and place-and-route functions. Chairs status meetings, communicates program updates to executive stakeholders, drives requirements closure, supports program management processes, and provides matrixed leadership to engineering managers.

Designs analog integrated circuit layouts from schematics using CAD tools and Cadence Virtuoso. Runs simulations and verification, debugs and refines layouts with analog IC designers, and collaborates with global engineering teams. Presents progress, communicates technical issues and solutions, and contributes to semiconductor projects from development through verification.

Owns analog and mixed-signal verification for broadband RF/TIA and high-speed communication ICs. Develops verification plans, test cases, coverage-focused testbenches, and simulations using industry-standard methodologies. Analyzes results, documents compliance, collaborates with circuit design and layout teams to resolve issues, and supports multiple CMOS and SiGe BiCMOS process nodes.

Assist with designing, testing, debugging, validating, and documenting electrical hardware for optical modules and AI platforms. Use lab equipment to evaluate hardware components, troubleshoot issues, and support verification activities. Maintain schematics, PCB layouts, and bills of materials. Candidates should be enrolled in a related bachelor’s or master’s program, understand electrical engineering and circuit design principles, and be familiar with CAD tools and electrical measurement methods.

Develop and support automated analog and mixed-signal CAD design flows, including parasitic extraction, physical verification, PDK validation, and post-layout processes. Build custom PCells, Pycells, GUI utilities, and automation tools across Cadence, Synopsys, and Siemens environments. Partner with analog designers and EDA vendors to resolve complex flow issues and establish CAD infrastructure for FinFET, BiCMOS, SiGe, and silicon photonics technologies.

Leads Marvell’s government affairs strategy in China, representing the company with central government ministries and industry stakeholders. Builds senior-level relationships, advises executives on policy and regulatory developments, supports export control and M&A review strategies, and translates Chinese technology, semiconductor, AI, and trade policies into business guidance. Coordinates with legal, communications, global government affairs, and business teams while assessing regulatory and geopolitical risks affecting China operations and AI-related opportunities.

Develop scalable embedded network software and SDK components for Marvell Teralynx switching products. Responsibilities include requirements gathering, architecture and design, implementation, unit and functional testing, maintenance, and solving complex technical problems. The role requires embedded switch/router software development using C, C++, and Python, with collaboration across distributed engineering teams.

Support chip power design by learning power estimation methodologies, performing analysis, identifying RTL and physical-design optimizations, developing automation, and exploring AI-based design-flow improvements. Collaborate with architecture, RTL, verification, physical design, and power teams while analyzing trends and presenting findings to the team.

Design and validate high-performance RF and analog circuits for optical communication ICs, including multi-tens-of-GHz transimpedance amplifiers, broadband receiver circuits, regulators, sensors, and control loops. Responsibilities include transistor-level design, transmission-line development, analog custom layout, silicon tape-out, lab evaluation, simulation-to-measurement correlation, post-silicon validation, qualification, production transition, and customer support. The role may also mentor designers, lead chips through production, and translate specifications into architectures.

The Senior Staff Auditor executes SOX compliance activities and leads operational audits. Responsibilities include documenting processes, conducting walkthroughs, testing internal controls, coordinating with external auditors, identifying risks and deficiencies, drafting reports, tracking remediation plans, and supporting audit automation, data analytics, and AI-enabled initiatives. The role requires collaboration with control owners, management, IT partners, and internal audit leadership.

Lead semiconductor ATE test engineering for characterization, production, and wafer sort using Advantest 93K and/or Teradyne platforms. Develop high-speed test hardware, test plans, test programs, and methodologies; convert simulation patterns to ATE formats; optimize test flows, yields, and test times; and collaborate with design, DFx, and product engineering teams.

Lead and execute ASIC physical design for complex SoCs, including floorplanning, power-grid design, place and route, clock-tree synthesis, timing closure, signal integrity, physical verification, and tapeout. Develop physical design methodologies and flows while collaborating with frontend, integration, customer, and global engineering teams. Use industry-standard Cadence and Synopsys tools alongside scripting languages for backend design and verification.

Supports hardware engineering activities across semiconductor product lifecycle stages, including requirements planning, supplier engagement, engineering analysis, repair and rebuild cycles, production testing, hardware transfers, cost reduction, quality improvement, and failure analysis. Completes a mentored engineering project focused on hardware deliverables or technical problem-solving and presents the results to engineering stakeholders.

Develop and optimize high-performance networking software for switch and PHY platforms. Responsibilities include control and data plane development, Layer 2/3 networking, packet processing, QoS, congestion control, telemetry, MACsec, SyncE, PTP, and hardware-software integration. Contribute to SONiC, SAI, OVS, and Linux kernel open-source projects, collaborate with hardware teams, participate in code reviews, and deliver complex technical projects independently.