Intern responsible for developing and testing firmware for high-speed transceivers, collaborating with a cross-functional team and managing software milestones.

The role involves managing product marketing for custom silicon solutions in datacenter environments, with an emphasis on AI systems, guiding product roadmap and market strategy.

The Firmware Engineer will design, implement, test, and enhance embedded firmware while collaborating with hardware and software teams to validate system performance and support product lifecycle.

As a Chip Lead, you will drive chip/chiplet programs, oversee design processes, ensure compliance, and mentor junior engineers while collaborating across teams.

The IP Program Manager leads cross-functional teams to manage IP development and delivery for Marvell's semiconductor products, ensuring successful execution from conception to production.

The Senior ASIC Product Engineer will develop test strategies, lead debug and characterization of ASIC products, and optimize test performance.

Lead automotive product development from a foundry perspective, optimizing yield and reliability while collaborating with internal teams and external partners.

The Staff Firmware Engineer will design, develop, and verify firmware features, collaborate on chip design, and deliver documentation and source code.

The Senior Staff IO Layout Engineer is responsible for layout execution, verification of I/O circuits, team mentoring, and cross-functional collaboration.

Seeking a Staff IO Layout Engineer for physical layout and verification of high-speed I/O circuits, mentoring team members, and coordinating with cross-functional teams.

The Director of Identity and Access Management will oversee IAM strategy, operations, and processes while driving innovation and efficiency across the organization.

The Staff Firmware Engineer will design, test, and maintain firmware for embedded systems, collaborating with hardware and software teams to optimize performance and reliability, while also participating in product lifecycle from inception to release.

Design and optimize analog mixed-signal layouts, lead layout projects, mentor junior engineers, and ensure quality standards are met while maintaining documentation.

Responsible for implementing and validating DFT/Test on custom ASIC/SoC designs, mentoring a team, and enhancing methodologies in DFT/Test.

The Principal Physical Design Engineer will work on physical design and methodology for high-performance processor chips, focusing on place and route flows and timing analysis.

The Senior Engineer will develop high-speed I/O circuits, support ESD reviews, implement guidelines, and contribute to various project tasks.

Design and verify high-speed I/O circuits and ESD solutions, collaborate with ESD leads and CAD teams, and perform layout quality checks.

Lead the go-to-market strategy for ethernet switching products in data centers, collaborating with engineering and sales to meet customer needs and drive revenue.

The role entails overseeing IP/Sub-System Verification, defining test plans, developing testbenches, executing design verification, and debugging simulation failures.

The role involves RTL coding, verification, micro-architecture design, power optimization, synthesis, and chip validation within the Automotive Ethernet domain.