Jobs at Marvell Technology

Leads global engineering applications and lab operations, defining modernization, cloud migration, integrated development platform, and Labs-as-a-Service strategies. Oversees engineering toolchains, lab provisioning, security, network architecture, governance, automation, resiliency, observability, and compliance. Partners with Engineering, IT, Security, and Facilities to standardize workflows, protect intellectual property, improve developer productivity, and enable scalable collaboration across global teams.

Develop accurate functional models and simulations for System-on-Chip designs within Marvell’s Virtual Platforms team. Collaborate with software and firmware teams, analyze simulation results, diagnose firmware issues, and promote virtual platform adoption. The role requires Python and C++ knowledge, understanding of firmware and software architecture, and familiarity with computer architecture; simulator experience with Virtualizer, Simics, QEMU, or gem5 is preferred.

Leads Marvell’s global trade compliance team across export controls, sanctions, imports, customs, classification, and trade facilitation. Architects scalable compliance systems and processes, oversees investigations and audits, manages metrics and corrective actions, supports M&A, partners with counsel on licensing and regulatory matters, and implements automation including AI tools. The role develops a global team, delivers training, collaborates across business functions, and travels internationally to support stakeholders and process improvements.

Design and develop low-level firmware and platform software for compute, storage, and ASIC systems. Build and maintain OpenBMC management firmware, drivers, platform services, telemetry, monitoring, and management protocols. Collaborate with hardware teams on platform bring-up, testing, validation, and debugging. Create automated test plans and contribute to firmware qualification and CI/CD pipelines.

Lead advanced packaging technology development for AI accelerators, networking, and HPC products. Define package architectures, chiplet topologies, substrates, interposers, power delivery, thermal envelopes, and reliability strategies. Conduct routing, signal integrity, power integrity, electromagnetic, mechanical, and thermal analyses. Develop proof-of-concept technologies, establish roadmaps, and drive productization, qualification, and volume readiness with silicon teams, OSATs, foundries, and suppliers.

Responsible for defining and implementing IT PMO strategy, managing project portfolios, overseeing program execution, and optimizing financial resources while ensuring stakeholder alignment and compliance with governance frameworks.

Lead development and maintenance of P&R flows and add-on CAD tools for advanced-node SoC designs. Deploy and support flows, integrate with CAD platform, debug timing/floorplan/power issues, interface with EDA vendors, and innovate solutions for design challenges while keeping up with process and tool evolution.

Leads a portfolio of semiconductor product programs from customer engagement and pre-tape-out planning through production, sustained manufacturing, and end-of-life. Owns program governance, schedules, costs, supply continuity, customer commitments, capacity strategy, supplier performance, risk mitigation, executive reporting, and lifecycle transitions. Manages and develops Supply Chain Program Managers while influencing engineering, operations, sales, marketing, quality, customers, and global manufacturing partners.

Supports senior field application engineers with customer schematic and layout reviews for optical modules and interconnect products. Assists with signal and power integrity simulations, product bring-up, performance testing, lab tuning, hardware/software debugging, customer issue resolution, and technical documentation. The internship provides hands-on exposure to PAM4 and coherent DSP technologies, optical communication systems, SerDes, and field application engineering workflows.

Supports customer optical-module firmware and software development, lab automation, module bring-up, TX/RX performance testing, hardware/software debugging, firmware flashing, register access, logging, compliance checks, and technical documentation. The intern works with senior field application engineers and customer teams on PAM4, coherent DSP, and optical technologies.

Own customer demand forecasting and revenue execution for major technology customers. Drive forecast accuracy, variance management, bookings, backlog, supply, allocation, logistics, and delivery issue resolution. Lead executive business reviews and translate customer demand signals into executable internal plans. Partner cross-functionally with Finance, Planning, Pricing, Legal, Supply Chain, and Sales while influencing teams without formal authority.

Leads complex, high-visibility, cross-functional semiconductor projects from initiation through completion, ensuring on-time, on-budget delivery. Presents dashboards, reports, and strategic updates to executives; manages stakeholders, risks, issues, and organizational change. Mentors project teams, improves methodologies and tools, drives process optimization, and aligns initiatives with business objectives.

Lead the physical design organization and RTL-to-GDSII implementation of advanced SoCs. Responsibilities include methodology development, synthesis, floorplanning, power planning, place and route, clock tree synthesis, timing and signoff, physical verification, tapeout execution, team leadership, hiring, mentoring, resource planning, cross-functional alignment, and EDA tool deployment.

Lead physical design methodology and automation for next-generation processor and ASIC chips. Provide technical leadership across RTL-to-GDSII implementation, synthesis, floorplanning, place and route, clock tree synthesis, timing closure, power and signal integrity analysis. Collaborate globally with RTL, verification, CAD, and EDA vendors; evaluate tools, influence technical roadmaps, resolve complex implementation issues, and mentor engineers.

Lead physical design and methodology for complex processor and ASIC chips. Drive RTL-to-GDS implementation, multi-voltage place-and-route, static timing, physical verification, integration, and design closure. Collaborate with digital, RTL, and analog teams, while providing technical direction and mentoring. Develop Shell, Python, and Tcl automation scripts to improve design productivity and robustness.

Defines next-generation AI networking switch ASIC architectures for hyperscale cloud and AI workloads. Leads architectural decisions, performance modeling, simulation, trade-off analysis, standards development, and roadmap direction. Collaborates with silicon, software, systems, product, and customer teams; represents Marvell in standards bodies and strategic discussions; and mentors engineering teams.

Develop embedded firmware for DSP hardware, create test code, manage software development flows, and debug issues with HW/SW teams.

Provide L2/L3 deskside and remote support for Windows and macOS; manage onboarding, provisioning, MDM enrollment, hardware asset lifecycle, IMACs, and IT procurement. Operate and administer Zoom Rooms and enterprise AV hardware, perform preventive maintenance and AV troubleshooting, coordinate vendors, support events, and maintain AV runbooks and documentation.

Support Storage Business Unit FP&A by building financial models, forecasting, and variance analysis. Drive new product investment planning, month-end accounting controls, project tracking, costing, dashboards, and cross-functional reporting. Partner with business leaders, support planning cycles, and mentor junior team members to deliver actionable financial insights.

Lead verification of storage IP and complex digital designs: develop verification plans, build and maintain testbenches, run functional and performance verification, debug simulations, collaborate with design teams, and mentor junior engineers.