Jobs at Marvell Technology

Design and verify analog/mixed-signal ICs (PLL, DLL, ADC/DAC, CTLE, regulators, amplifiers, TX/RX, CDRs) using SPICE/Spectre/MATLAB. Architect circuits, implement designs, optimize low-power/high-speed techniques, and collaborate with system architects and global teams to deliver CMOS transceiver/SERDES products.

Architect and implement production-quality RTL for high-speed interfaces (UCIe/HBM and others). Own micro-architecture, RTL coding, synthesis, CDC/RDC and lint flows, and partner with verification and bring-up teams. Provide technical leadership, mentor junior engineers, participate in design reviews, and ensure IP quality, robustness, and reusability for silicon-proven IPs/SoCs.

Develop, integrate, and test network and cryptographic protocols and embedded firmware using C/C++/Python. Build automation and regression frameworks, prototype software for future products, research AI models, and collaborate with silicon and verification teams. Work with Linux, networking tools, and embedded system concepts.

Develop and document SDK software features, deliver releases and sample code, troubleshoot complex SW/API/GUI issues, support customer integration and lab trials, create technical collateral, and collaborate with silicon, validation, and marketing teams to drive product adoption.

The Principal Test Engineer will lead development of ATE test solutions, innovate high-speed testing hardware, craft test plans, and optimize test flows while collaborating with cross-functional teams.

The Senior Staff Engineer will design and validate high-performance RF/Analog circuits, specifically Transimpedance Amplifiers and various analog circuits, collaborating across teams to ensure successful production.

Design, verify, and evaluate digital circuits for high-speed communication ASICs. Develop ASIC specs and micro-architecture, design RTL for PHY transceivers, perform verification, synthesis, timing/PPA analysis, and support post-silicon debug and chip bring-up.

The Principal Engineer will architect simulation test benches, develop and execute test plans, debug failures, and mentor junior engineers in verifying chip designs.

Responsible for the design and validation of FET and BiCMOS circuits for high-speed broadband ICs and optical interface chips. Collaborate on post-silicon validation and transition to mass production.

Lead verification for advanced semiconductor designs. Responsibilities include developing test plans, UVM environments, automation scripting, and mentoring junior engineers.

Define and develop verification testbench architecture and components, create verification test plans, and work collaboratively on chip design verification with a focus on DDR/LPDDR/HBM technologies.

The role involves developing high-performance analog/mixed-signal ICs, measuring IC performance, and debugging designs across various advanced technologies.

Lead development and automation of physical verification CAD/EDA flows (DRC/LVS) using Synopsys ICV and Calibre, support tape-outs and foundry interfaces, integrate and optimize EDA tools, develop validation procedures and documentation, and mentor/lead cross-functional teams.

The Principal Engineer will lead DFT architecture on multi-die designs, mentor engineers, and implement DFT methodologies for complex ICs.

The role involves planning, designing, and verifying digital circuits in SerDes IP, coordinating with cross-functional teams to deliver high-speed communication solutions.

As a Senior Staff DFT Engineer, you will lead DFT strategies, improve methodologies, validate designs, and support post-silicon debugging in a global team environment.

The role involves verifying designs for advanced storage technologies, developing test plans, creating testbenches, and mentoring junior engineers.

Support customers integrating Marvell Ethernet PHYs through schematic review, board bring-up and debugging, lab/field trials, troubleshooting, technical training, sales support, cross-functional collaboration, and creation of application notes and technical collateral.

Lead implementation of DFT/Test for complex ASIC/SoC and chiplet designs using Tessent and related EDA tools. Define DFT architecture, run insertion flows, generate patterns, support STA constraints, and drive post-silicon bring-up and debug. Mentor a small DFT team and enhance methodologies and tools across multi-die custom compute designs.

The Principal Hardware Engineer will design, develop, and test electrical hardware for optical modules, mentor junior engineers, and collaborate with teams for hardware specifications while ensuring effective troubleshooting and validation of components.