This role involves physical design of complex chips, integrating designs across disciplines, mentoring juniors, and scripting for automation.

The Firmware Intern will develop embedded firmware, create technical documentation, and support testing across hardware and firmware while collaborating with cross-functional teams.

Design micro-architecture for chips, implement low-power RTL, collaborate on verification and physical design, and support silicon bring-up.

Design and develop system software for network and storage systems using C/C++ and Python, providing technical guidance to junior engineers and prototyping new modules.

Develop advanced microelectronic packages for semiconductors, focusing on electrical design, signal/power integrity, and supplier collaboration.

Responsible for designing high-speed optical transceiver circuits, overseeing layout activities, validating models, and mentoring junior designers.

Lead the micro-architecture and RTL development for advanced SoC designs, ensuring functional correctness and integration across multiple systems while collaborating with various engineering teams.

The role involves planning, designing, and verifying digital circuits in SerDes IP, coordinating with cross-functional teams to deliver high-speed communication solutions.

As a Software Engineer Intern at Marvell, you'll develop functional models for SoC architectures, write embedded software, and enhance test automation while collaborating with the engineering team.

As a Staff Analog Layout Engineer, you will collaborate with global teams to run simulations and deliver high-speed analog circuits, ensuring project specifications are met through the development cycle.

As a Principal Test Engineer, lead the development of ATE test solutions, innovate high-speed testing hardware, and create comprehensive test plans while collaborating with cross-functional teams.

The Staff Firmware Engineer will design, implement, and optimize SSD firmware features, perform failure analysis, and collaborate across teams to ensure effective firmware development and deployment.

The Principal Engineer will lead DFT architecture on multi-die designs, mentor engineers, and implement DFT methodologies for complex ICs.

The Analog Layout Senior Staff Engineer will lead the design and verification of high-speed analog circuits, collaborating globally on various projects, and taking full ownership of the development cycle.

The role involves simulation, modeling, performance analysis, and tooling for AI/ML workloads, focusing on hardware/software co-design in advanced computing environments.

Lead the architecture and design of complex SoCs, guiding cross-functional teams through specification, verification, and integration processes while mentoring junior members.

As a Senior Distinguished Engineer, lead the architecture of high-performance networking ASICs, foster innovation, and mentor engineers. Collaborate with cross-functional teams to enhance scalable data infrastructures for AI and cloud applications.

The Principal Test Engineer will lead development of ATE test solutions, innovate high-speed testing hardware, craft test plans, and optimize test flows while collaborating with cross-functional teams.

As a Senior Staff Engineer in Analog Layout, you will run simulations, collaborate across global teams, and deliver analog circuits through the full development cycle, ensuring high standards and effective communication.

Lead the delivery of Marvell's marketing technology initiatives, oversees customer-facing applications, and drives operational stability while communicating technical solutions to marketing needs.