Senior STA Timing Engineer

Meet the team

Join our dynamic Test Timing Engineering team, a group of passionate experts dedicated to ensuring robust and accurate timing constraints for advanced chip designs. Our work is critical to the success of the broader silicon design process, enabling efficient test and verification of complex integrated circuits. The team is mid-sized, blending seasoned engineers with fresh perspectives, fostering a collaborative and supportive environment. You’ll find an atmosphere of innovation, continuous learning, and strong cross-functional collaboration, all driven by a commitment to technical excellence. If you thrive on solving challenging problems and making a tangible impact on product quality, you’ll feel right at home here.

As a Test Timing Engineer, you will play a pivotal role in developing and validating timing constraints that ensure the accuracy and reliability of advanced chip designs.

• Own the creation and validation of timing constraints at block, sub-chip, and full-chip levels in various test modes.

• Perform quality checks, including identifying duplicated constraints and verifying unconstrained endpoints, to drive robust timing analysis.

• Develop and enhance methodologies, guidelines, and checklists to streamline static timing analysis (STA) workflows.

• Collaborate with cross-functional teams to resolve timing and design flow issues, accelerating project execution.

• Implement and maintain SDC flows and validation processes to ensure compliance and accuracy across all design stages.

• Bachelor’s degree in electrical or computer engineering (or equivalent field) with 8+ years of relevant work experience or Master’s degree in electrical or computer engineering (or equivalent) with 6+ years of relevant experience.

• Demonstrated experience developing block/full-chip SDC in test modes (scan shift, scan capture, ATPG capture).

• Proficiency in Static Timing Analysis (STA) and hands-on experience with tools such as PrimeTime.

• Programming proficiency in at least two scripting languages (e.g., Perl, TCL, Python, Makefile).

• Proven track record in SDC validation, timing exception handling, and STA flow development.

• Master’s degree in electrical or computer engineering (or equivalent) with 6+ years of relevant experience.

• Experience debugging and analyzing timing constraints for DFT modes (scan shift/capture, BIST)

• Prior hands-on experience with SDC debugging and STA tools (Synopsys GCA/TCM/PrimeTime)

• Experience with synthesis tools, especially Synopsys Fusion Compiler, and Tessent DFT insertion

• Strong communication skills and proven ability to work collaboratively within cross-functional teams

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