Senior RTL Design Lead

This role is for one of the Weekday's clients

Salary range: Rs 2000000 - Rs 7000000 (ie INR 20-70 LPA)

Experience: 5+ yrs

Location: Bengaluru

Job Type: full-time

We are seeking an experienced RTL Design Lead with a strong passion for hands-on RTL development and technical leadership. This role is ideal for professionals with extensive experience in ASIC/SoC design, Verilog, SystemVerilog, and RTL coding, who enjoy translating complex architectural concepts into high-quality, synthesizable hardware designs.

As an RTL Design Lead, you will own the design and microarchitecture of complex IPs and subsystems, driving the complete RTL development lifecycle from architectural specifications to RTL sign-off. You will work closely with Architecture, Verification, DFT, Physical Design, and STA teams to deliver high-performance, power-efficient, and area-optimized silicon solutions. Beyond technical execution, you will mentor engineering teams, establish RTL design best practices, and lead by example through active coding and technical excellence.

• Lead the RTL design and microarchitecture development of complex ASIC/SoC IPs and subsystems.
• Develop high-quality, synthesizable RTL using Verilog and SystemVerilog while following industry-standard coding methodologies.
• Translate architectural specifications into efficient and scalable RTL implementations that meet performance, power, and area (PPA) targets.
• Drive RTL quality through code reviews, lint analysis, CDC verification, synthesis checks, and design validation.
• Analyze and resolve functional, timing, and design-related issues throughout the development lifecycle.
• Collaborate closely with Verification, DFT, Physical Design, STA, and Architecture teams to ensure successful project execution.
• Review technical specifications and provide architectural recommendations to improve design quality and implementation efficiency.
• Define and promote RTL coding standards, design methodologies, and engineering best practices across the team.
• Mentor junior engineers through technical guidance, code reviews, and knowledge sharing while maintaining active involvement in development.
• Support synthesis, design constraint development (SDC), timing closure, and overall ASIC implementation activities.
• Contribute to continuous process improvements that enhance design quality, productivity, and development efficiency.

• Bachelor's or Master's degree in Electronics, Electrical Engineering, or a related discipline.
• 10+ years of hands-on experience in ASIC/SoC RTL Design with strong expertise in RTL Coding.
• Advanced proficiency in Verilog and SystemVerilog for developing production-quality RTL.
• Strong understanding of digital design fundamentals, including finite state machines (FSMs), pipelining, clock domain crossing (CDC), reset strategies, and synchronization techniques.
• Proven experience in microarchitecture development and translating architectural specifications into robust RTL implementations.
• Hands-on experience with linting, CDC analysis, synthesis, and Design Constraints (SDC).
• Familiarity with the complete ASIC design flow, from specification through implementation and tape-out.
• Experience working with industry-standard EDA tools such as Synopsys Design Compiler, SpyGlass, PrimeTime, or equivalent solutions.
• Knowledge of high-speed protocols such as AMBA/AXI, PCIe, DDR, Ethernet, or USB is an added advantage.
• Exposure to low-power design methodologies, formal verification, and static timing analysis (STA) concepts is desirable.
• Strong analytical, debugging, communication, and leadership skills with the ability to mentor teams while remaining an active individual contributor.