IP / SoC RTL Senior / Lead Design Engineer

Posted 3 Days Ago
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Bengaluru, Bengaluru Urban, Karnataka, IND
In-Office
Senior level
Information Technology • Professional Services • Consulting
The Role
Design and develop IP/sub-system micro-architecture and RTL; prepare block-level timing constraints; integrate IP/sub-systems; perform basic verification in IP verification environments or on FPGA; work with synthesis, timing, CDC, lint, and simulation tools; support multi-clock and asynchronous interfaces.
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Company Description

Finite HR Consulting

Job Description

Our Client SeviTech is looking for IP / SoC RTL Senior / Lead Design Engineer

About our Client: http://sevitechsystems.com/

Job Designation: IP / SoC RTL Senior / Lead Design Engineer

Job Location: Bangalore

Job Type: Permanent 

 IP / SoC RTL Senior / Lead Design Engineer

Job Description:

• You will be responsible for IP / sub-system level micro-architecture development and RTL coding.

• Prepare block/sub-system level timing constraints.

• Integrate IP/sub-system.

• Perform basic verification either in IP Verification environment or FPGA.

Desired Skills and Experience:

• B. Tech. or M. Tech. with 6 to 8 years of experience.

• Experience in Logic design / micro-architecture / RTL coding is a must.

• Expertise in Verilog is a must.

• Should have knowledge of AMBA protocols - AXI, AHB, APB.

• Experience in Synthesis / Understanding of timing concepts for ASIC is required.

• Experience in design of DDR / USB / PCIe controller or such complex protocols is a plus.

• Hands on experience in Multi Clock designs, Asynchronous interface are a must.

• Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required.

• Knowledge of low power concepts and experience is a plus.

This is an Immediate Opportunity candidate with less than one month notice will be 

preferred.

Please ignore this mail if the above profile doesn’t match with your current Job Role.

Thank you for your Valuable Time

Hoping for a Prompt Response!!!

Qualifications

MTec / Btec

Additional Information

Skills Required

  • B.Tech or M.Tech degree with 6-8 years experience
  • Experience in logic design, micro-architecture, and RTL coding
  • Expertise in Verilog
  • Knowledge of AMBA protocols (AXI, AHB, APB)
  • Experience in synthesis and understanding of ASIC timing concepts
  • Hands-on experience with multi-clock designs and asynchronous interfaces
  • Experience with tools used across ASIC development (lint, CDC, simulation)
  • Ability to perform basic verification in IP verification environments or on FPGA
  • Experience designing DDR, USB, or PCIe controllers
  • Knowledge of low power design concepts
  • Immediate availability or notice period <1 month
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The Company
0 Employees

What We Do

FiniteHR is a Human Capital Management organization, has been in business since 2014 in Hyderabad, serving IT and non IT clients in Domestic and International markets. They are a team of dedicated professionals with expertise in recruiting professionals and specialized experts across North America, Asia, Middle East and Europe, acting as an ideal outsourcing partner for recruitment and staffing services.

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