Senior Product Development Engineer

Posted 23 Days Ago
Be an Early Applicant
Santa Clara, CA, USA
In-Office
136K-259K Annually
Senior level
Artificial Intelligence • Computer Vision • Hardware • Robotics • Metaverse
The Role
Lead ATE bring-up, silicon characterization, reliability stress testing, and failure analysis for SoCs. Drive test strategies (DFT, scan, MBIST, IOBIST), debug test yield issues from NPI to HVM, define reliability stress conditions, and coordinate FA with foundry and vendors to close failures.
Summary Generated by Built In

NVIDIA is a leading provider of cutting-edge technology solutions in the semiconductor industry! We specialize in the development and enhancement of integrated circuits (ICs) for a wide range of applications, including consumer electronics, automotive, and telecommunications. Our team is dedicated to innovation, quality, and pushing the boundaries of what is possible in the world of microelectronics. We are seeking a highly skilled and motivated Product Development engineer to drive bring up of innovative SOCs through collaboration with external vendors, design and production teams.

What you'll be doing:

  • Serve as the primary technical interface between ATE and internal partners for test strategy, ATE bring-up, and silicon qualification, driving alignment on PDE char plan, DFT coverage & engineering FA for root-cause & preventive action.

  • Define & drive PDE Silicon characterization plans covering key tests (scan, mbist, IObist, functional) & features covering analog mixed-signal designs.

  • Ensure robust test yields are achieved going from NPI to high volume manufacturing. Test yield distractors are debugged & resolved systematically to achieve the target yields.

  • Finalize overall reliability QUAL stress conditions based on product usage covering embedded, commercial, industrial & automotive needs.

  • Drive all aspects of stress testing of silicon from wafer-level to pkg. level covering silicon+pkg level reliability qualification & testing associated with it.

  • Ensure Burn-in needs for the product are evaluated, supported & deployed in NPI & MP phase.

  • Analyze & automate aging data from HTOL/pkg. qual/DVS testing & guide the team on further debug steps for further failure analysis.

  • Drive true failures from reliability evaluation to closure w/ final FA report, working with FA & foundry teams.

What we need to see:

  • Bachelor's degree in Electrical Engineering (or equivalent experience) and 5+ years of relevant experience

  • Analytical and problem-solving skills, especially in solving ATE test failures with root-cause analysis.

  • Hands on experience of debugging chip level failures on ATE platform & drive FA to closure.

  • Good understanding & experience of SOC / Silicon qualifications covering exposure to HTOL, ESD/LU, HTS, TC, HAST etc.

  • Exposure to both Teradyne and Advantest platforms is a plus

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 258,750 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until June 26, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Skills Required

  • Bachelor's degree in Electrical Engineering or equivalent experience with 5+ years relevant experience
  • Hands-on experience debugging chip-level failures on ATE platforms and driving failure analysis to closure
  • Experience with silicon characterization including scan, MBIST, IOBIST and analog mixed-signal features
  • Good understanding and experience of SOC/silicon qualifications and reliability testing (HTOL, ESD/LU, HTS, TC, HAST)
  • Analytical and problem-solving skills, especially for ATE test failures and root-cause analysis
  • Exposure to Teradyne and Advantest platforms
  • Experience managing NPI to high-volume manufacturing test yield improvement

NVIDIA Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about NVIDIA and has not been reviewed or approved by NVIDIA.

  • Equity Value & Accessibility Equity awards and a discounted ESPP are highlighted as core parts of total compensation, enabling employees to share in the company’s success. Stock-based compensation and the two-year lookback ESPP are consistently described as especially valuable.
  • Healthcare Strength Health coverage is portrayed as robust, with comprehensive medical, dental, and vision options alongside mental health support and on-site care resources. Employer HSA contributions and wellness perks reinforce the depth of the offering.
  • Retirement Support Retirement programs are depicted as strong, featuring a meaningful 401(k) match with Roth options and support for Mega Backdoor Roth contributions. These elements position long-term savings as a notable advantage of the total rewards package.

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The Company
HQ: Santa Clara, CA
21,960 Employees
Year Founded: 1993

What We Do

NVIDIA’s invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing — with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. Today, NVIDIA is increasingly known as “the AI computing company.”

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