Jobs at NXP Semiconductors

Provide worldwide technical support for customers developing products with NXP i.MX application processors. Resolve technical inquiries, review schematics and PCB layouts, assist with application development and training, and create technical documentation. Collaborate with product, marketing, and engineering teams to improve customer satisfaction, accelerate design-ins, and communicate customer requirements internally.

Design and implement AI/ML compiler technologies for embedded ARM and RISC-V hardware using C++ and LLVM. Develop MLIR and graph compiler features, optimize model lowering, fusion, tiling, scheduling, code generation, and inference performance. Collaborate with hardware architects, ML researchers, and global development teams to support automotive system-on-chip platforms. Analyze generated code with simulators and profilers while contributing to open-source compiler technologies.

Performs wire bonding processes on quality-hold materials, collaborates with engineering to improve wire bonding techniques, and troubleshoots process issues to reduce production downtime. Requires an engineering-related diploma, strong attention to detail, and technical troubleshooting skills. Prior wire bonding experience is preferred.

Performs wire bond process tasks on quality-hold materials, collaborates with engineering to improve processes and techniques, and helps troubleshoot wire bond issues to reduce production downtime. Requires an engineering-related diploma, strong attention to detail, and technical troubleshooting skills. Prior wire bond process experience is preferred.

Develop AI/ML compiler technologies for embedded ARM and RISC-V processors, optimizing models through graph compilation, lowering, fusion, tiling, scheduling, code generation, and performance analysis. The role involves C++ and LLVM/MLIR development, collaboration with hardware architects and ML researchers, compiler support for automotive SoCs, and contribution to open-source projects.

Design and implement AI/ML compiler technologies for embedded ARM and RISC-V processors using C++, Python, LLVM, and MLIR. Optimize machine learning models through graph-level transformations, lowering, fusion, tiling, scheduling, and code generation for automotive SoCs. Collaborate with hardware architects, ML researchers, compiler consumers, and global development teams to improve inference performance and compiler quality.

Design and implement AI/ML compiler technologies for embedded ARM and RISC-V processors using C++, LLVM, and MLIR. Optimize machine learning models through graph-level transformations, lowering, fusion, tiling, scheduling, code generation, and performance analysis. Collaborate with hardware architects, ML researchers, compiler consumers, and global development teams to deliver production compiler features for automotive SoCs.

Develop AI/ML compiler technologies for embedded hardware using C++ and LLVM, optimizing models for high-performance inference across semiconductor platforms. Build compiler features for ARM and RISC-V processors, including graph optimizations, model lowering, code generation, and optimization pipelines. Collaborate with architecture teams, internal tool users, and global development teams throughout design, development, and deployment.

Design and implement AI/ML compiler technologies for embedded ARM and RISC-V processors. Develop LLVM and MLIR compiler features, optimize graph-level workloads through lowering, fusion, tiling, and scheduling, and improve code generation performance across semiconductor platforms. Collaborate with hardware architects, ML researchers, compiler consumers, and global development teams. Analyze generated code using simulators and profilers while contributing production-quality C++ and Python code to compiler frameworks.

Lead development of test programs and test hardware for new semiconductor products, support ATE-based qualification and characterization, drive test cost and yield improvements, manage program changes and transfers, and coordinate cross-functional stakeholders to meet quality, cost, and delivery targets.

Coordinate and manage Safe Launch activities for new semiconductor products, monitor ramp-up performance, investigate quality and manufacturability issues, drive root-cause analysis and corrective actions, maintain launch tracking systems, and support continuous improvement and cross-functional NPI efforts.

Leads complex Digital IP and subsystem development programs from planning through release and SoC integration readiness. Manages integrated plans, schedules, dependencies, risks, resources, deliverables, and release criteria while coordinating architecture, design, verification, validation, software, and integration teams. Provides executive visibility through technical reviews, dashboards, KPIs, metrics, status updates, risk escalation, and decision management. Supports portfolio planning, resource prioritization, capacity management, and cross-functional execution across multiple product lines.

Provides technical leadership for digital IP verification, including verification planning, UVM testbench development, constrained-random and directed testing, coverage analysis, assertions, formal verification, debugging, and root-cause analysis. Mentors engineers and promotes zero-defect verification practices for automotive and microcontroller semiconductor products.

Own end-to-end physical design implementation for complex SoC and IP blocks from netlist through GDSII. Responsibilities include floorplanning, power planning, placement, CTS, routing, timing closure, PPA optimization, physical verification, IR-drop and electromigration analysis, DRC/LVS closure, ECOs, tapeout support, methodology automation, cross-functional collaboration, design reviews, and mentoring junior engineers.

Leads NXP’s China marketing and communications team, translating business and global priorities into measurable campaigns, brand positioning, executive communications, reputation management, thought leadership, and stakeholder engagement. Builds relationships with media, analysts, influencers, developers, partners, universities, and government stakeholders. Drives AI-enabled digital customer journeys, content, events, and ecosystem engagement across automotive, industrial, and consumer markets while measuring business and communications impact.

Lead physical design implementation and signoff for complex ASIC SoC and IP blocks in advanced technology nodes. Responsibilities include floorplanning, power grid design, placement, optimization, clock tree synthesis, routing, timing closure across MCMM scenarios, DRC/LVS signoff, IR drop and electromigration compliance, congestion and crosstalk debugging, ECO execution, cross-functional collaboration, and scripting-based methodology improvements.

Owns the strategy, development, positioning, and go-to-market execution for a Battery Management Systems semiconductor portfolio. Leads cross-functional collaboration across engineering, sales, applications, and operations; engages customers in market needs, design-ins, quotations, samples, and documentation; and drives product launches and competitive differentiation. Requires strong semiconductor and electrical systems knowledge, stakeholder influence, resilience, and global travel.

Provides expert-level functional safety assessments and peer reviews for safety-related automotive semiconductor software and SoC products. Performs ISO 26262 assessments, safety concept reviews, and safety analyses including FTA, SW FMEA, and DFA. Drives safety software innovation, promotes functional safety culture, aligns technical and business stakeholders, and supports system safety solution development. Domestic and international travel is required.

Performs RTL synthesis and front-end implementation for digital ASIC/SoC designs, optimizing timing, power, and area. Develops SDC constraints, conducts static timing analysis and formal equivalency verification, and supports timing closure. Automates synthesis and analysis flows using Tcl, Python, and Perl. Collaborates with RTL, DFT, and physical design teams, evaluates CAD tools, and documents methodologies and results.

Lead pre-silicon verification of digital IP modules and subsystems. Develop verification plans, UVM environments, test cases, stimulus, assertions, and regression tests. Execute simulations across RTL, power-aware RTL, gate-level, FPGA, and emulation platforms; debug designs and analyze code and functional coverage. Collaborate with hardware, firmware, software, architecture, and systems engineering teams.