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Life at Intel
About the team and organization: Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP) organization. DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services that allow Intel Foundry customers to deliver winning products to the marketplace. Your work will directly enable design teams to get to the market faster with leadership products based on innovative technologies. As a member of CDMG you will be at the forefront of co-optimizing Intel's state-of-the-art process technology which allows customers with diverse design needs to enable best-in-class products for data-centric applications.
As a semiconductor device modeling engineer, you will be playing a key role to support compact modeling activities for Intel's new technologies.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
• Bachelor's degree in Electrical Engineering or a related discipline and 5+ or
Master's degree in Electrical Engineering or a related discipline and at least 3 years of industry experience in the semiconductor field; or Ph.D. in Electrical Engineering or a related discipline.
• Graduate coursework or research experience in semiconductor device physics or 5+ years of work experience in Semiconductor device physics.
• 1+ years' experience Python scripting for data analysis, automation and documentation.
Preferred Qualifications
• Ph.D. in Electrical Engineering or a related discipline with 3+ years of industry experience in the semiconductor field.
• Proficiency with extraction tools (e.g., ICCAP, MBP) and commercial simulators such as HSPICE, Spectre, etc.
• Hands-on experience with BSIM-CMG and other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA) including experience in one or more of the following areas:
Experience developing Layout-dependent effects (LDE) for FinFET or GAAFET technologies and their impact on circuit performance.
Development of methodologies for device targeting (e.g., transistors) and benchmarking circuits (e.g., ring oscillators), including corners and statistical variation models.
Modeling using Open Model Interface (OMI).
Strong understanding of process flow, layout, and basic circuit design/simulation.
Modeling self-heating effects and their influence on device and circuit performance.
Proven capability to collaborate across multiple teams and geographies.
Experience with machine learning algorithms and their application is data analysis and compact model development.
Benefits at Intel
Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, California, Santa ClaraPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's degree in Electrical Engineering or related discipline and 5+ years industry experience
- Master's degree in Electrical Engineering or related discipline and at least 3 years industry experience
- Ph.D. in Electrical Engineering or related discipline
- Graduate coursework or research experience in semiconductor device physics or 5+ years work experience in semiconductor device physics
- 1+ years Python scripting for data analysis, automation and documentation
- Proficiency with extraction tools (e.g., ICCAP, MBP) and commercial simulators such as HSPICE, Spectre
- Hands-on experience with BSIM-CMG and other compact models for transistor modeling at advanced nodes (FinFET, GAA)
- Experience developing layout-dependent effects (LDE) for FinFET or GAAFET and analyzing circuit impact
- Development of methodologies for device targeting and benchmarking circuits, including corners and statistical variation models
- Modeling using Open Model Interface (OMI)
- Strong understanding of process flow, layout, and basic circuit design/simulation
- Modeling self-heating effects and their influence on device and circuit performance
- Proven capability to collaborate across multiple teams and geographies
- Experience with machine learning algorithms applied to data analysis and compact model development
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
Intel Insights
What We Do
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone.
