Principal SoC System Architect

Posted 19 Days Ago
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Raanana, ISR
In-Office
Expert/Leader
3D Printing
The Role
Owns system-level and full-chip architecture for advanced MPU and SoC products. Defines scalable architectures, subsystem interfaces, performance and resource budgets, workload models, HW/SW partitioning, and implementation trade-offs. Leads architecture from product definition through silicon bring-up and validation while aligning product, engineering, software, verification, implementation, and customer-facing teams. Requires extensive experience with integrated application-processor SoCs, quantitative performance analysis, heterogeneous compute, memory, interconnect, power, security, and platform integration.
Summary Generated by Built In
Job Description

Own the system-level and full-chip architecture of next-generation high-end MPU products targeting high-performance applications such as Robotics and Physical AI, industrial networking and control, advanced Vision, multimodal AI processing, and other advanced embedded systems.

Define scalable and reusable SoC architectures that integrate heterogeneous compute, Camera/Vision, AI, HMI/Display, memory and interconnect, connectivity, security, safety, and platform-management capabilities into coherent, software-enabled products across multiple market and performance tiers.

Translate product strategy, customer use cases, representative workloads, and technology capabilities into architectural decisions that balance performance, power, thermal behavior, area, cost, scalability, software compatibility, implementation feasibility, risk, and time-to-market.

Work across a global, multidisciplinary organization spanning Product, business, architecture, HW, SW/FW, verification, implementation, and customer-facing teams. Engage directly with Product Line and Engineering leaders from Director through Vice President level to formulate architecture alternatives, communicate technical and business trade-offs, build alignment, and drive major decisions to timely closure.

Principal Accountabilities

  • Own and drive the system-level and full-chip architecture of next-generation MPU products, from early product definition through silicon bring-up and product validation. Develop clear architecture proposals, align technical and business stakeholders, and drive major decisions to timely closure.
  • Translate customer use cases, workloads, market requirements, and product strategy into scalable and reusable SoC architectures across multiple product tiers.
  • Define the full-chip SoC composition, system data and control flows, shared resources, subsystem interfaces, and integration architecture.
  • Define system requirements and allocate performance, power, thermal, memory, bandwidth, latency, QoS, area, and cost budgets across subsystems. Drive convergence and resolve conflicts.
  • Define representative concurrent workloads and use quantitative analysis to identify bottlenecks, validate architectural choices, and drive system-resource convergence.
  • Drive and enable HW/SW co-development through early stakeholder engagement and clear definition of system partitioning, interfaces, requirements, assumptions, and constraints.
  • Drive architecture trade-offs and implementation-feasibility assessments across performance, power, area, cost, software impact, implementation risk, schedule, and technology constraints.

Qualifications

Essential

  • Extensive experience in the top-level architecture of highly integrated MPU or Application Processor-class SoCs, with demonstrated ownership from product and use-case definition through implementation, silicon bring-up, and product validation.
  • Broad knowledge of heterogeneous compute, memory hierarchy, cache coherency, interconnect, shared resources, high-speed I/O, system control, power management, security, software-visible architecture, and platform integration.
  • Ability to translate customer use cases and concurrent workloads into system data and control flows, requirements, KPIs, resource budgets, and architecture decisions.
  • Experience analyzing system performance through quantitative modeling, identifying bottlenecks and resource constraints, and adjusting the architecture or system configuration accordingly.
  • Ability to incorporate software and firmware requirements, execution constraints, and ecosystem considerations into HW/SW partitioning, interfaces, and SoC architecture decisions.
  • Experience assessing full-chip feasibility and driving trade-offs across performance, power, thermal behavior, area, cost, implementation risk, and schedule.
  • Strong technical leadership and communication skills, with the ability to structure incomplete requirements, develop rigorous proposals, and drive alignment across global teams and senior stakeholders.

Desirable

  • Experience with high-performance MPU or application-processor SoCs supporting Robotics, Physical AI, industrial networking and control, advanced Vision, multi-modal AI, or similarly complex workloads.
  • Deep expertise in a major SoC architecture domain, such as compute, memory and interconnect, coherency, system performance, real-time processing, power and thermal architecture, security, or full-chip integration.
  • Experience defining scalable and reusable SoC architectures across product families or performance and cost tiers.
  • Experience with functional-safety or mixed-criticality SoC architecture, including isolation, fault containment, diagnostics, and relevant ISO 26262 or IEC 61508 considerations.

Qualifications

Essential

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.

Desirable

  • Advanced degree, relevant patents, publications, standards participation, or recognized technical leadership in SoC or system architecture.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Skills Required

  • Extensive experience architecting highly integrated MPU or application-processor-class SoCs from product and use-case definition through implementation, silicon bring-up, and product validation.
  • Broad knowledge of heterogeneous compute, memory hierarchy, cache coherency, interconnect, shared resources, high-speed I/O, system control, power management, security, software-visible architecture, and platform integration.
  • Ability to translate customer use cases and concurrent workloads into system data and control flows, requirements, KPIs, resource budgets, and architecture decisions.
  • Experience analyzing system performance through quantitative modeling, identifying bottlenecks and resource constraints, and adjusting architecture or system configuration.
  • Ability to incorporate software and firmware requirements, execution constraints, and ecosystem considerations into HW/SW partitioning, interfaces, and SoC architecture decisions.
  • Experience assessing full-chip feasibility and driving trade-offs across performance, power, thermal behavior, area, cost, implementation risk, and schedule.
  • Strong technical leadership and communication skills, including structuring incomplete requirements, developing rigorous proposals, and driving alignment across global teams and senior stakeholders.
  • Experience with high-performance MPU or application-processor SoCs supporting robotics, Physical AI, industrial networking and control, advanced vision, multimodal AI, or similarly complex workloads.
  • Deep expertise in a major SoC architecture domain such as compute, memory and interconnect, coherency, system performance, real-time processing, power and thermal architecture, security, or full-chip integration.
  • Experience defining scalable and reusable SoC architectures across product families or performance and cost tiers.
  • Experience with functional-safety or mixed-criticality SoC architecture, including isolation, fault containment, diagnostics, and ISO 26262 or IEC 61508 considerations.
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
  • Advanced degree, relevant patents, publications, standards participation, or recognized technical leadership in SoC or system architecture.

Renesas Electronics Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Renesas Electronics and has not been reviewed or approved by Renesas Electronics.

  • Fair & Transparent Compensation — Feedback suggests pay is generally fair-to-good across many roles, with base pay aligned to prevailing market levels in multiple U.S. locations. Engineering and leadership tracks can be competitive on total compensation, reinforcing a sense that pay can meet market expectations in key job families.
  • Healthcare Strength — Feedback suggests core medical, dental, and vision coverage is solid and well-regarded by employees. Day-one eligibility in U.S. roles is described, supporting confidence in access and continuity of care.
  • Leave & Time Off Breadth — Feedback suggests PTO, paid holidays, sick time, and parental leave provide a comprehensive time-off framework. Company initiatives like Renesas Day and meeting-light Focus Fridays further support time away and balance.

Renesas Electronics Insights

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The Company
HQ: Tokyo
10,040 Employees

What We Do

We're the world's leading semiconductor manufacturer. Our mission is to make our lives easier and a world that's safer, healthier, greener, and smarter.

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