The WSSI (Windows Silicon System Integration) team is looking for an experienced Silicon Design Verification Team Lead to lead verification for complex silicon subsystems that are part of advanced solutions delivered in Windows client products.
This is an opportunity for an excellent DV leader to combine people leadership with meaningful hands-on technical contribution. You will lead a silicon engineering team that includes design verification, silicon design, and physical design engineers, while serving as the technical anchor for the team's verification strategy, execution, and quality.
The team works on complex security-oriented silicon subsystems that require rigorous pre-silicon verification and close collaboration with architecture, design, firmware, system engineering, and physical design partners to deliver robust silicon quality.
We are looking for a leader who is passionate about building excellent teams, driving rigorous execution, contributing hands-on to complex verification challenges, and continuously improving verification methodologies - including applying modern AI-assisted techniques to improve productivity, debug efficiency, and verification quality.
Responsibilities
- Lead, grow, and mentor a silicon engineering team that includes design verification, silicon design, and physical design engineers, while fostering a culture of technical excellence, ownership, collaboration, and continuous learning.
- Own and drive the verification strategy for complex silicon subsystems from planning through execution, closure, and emulation readiness.
- Provide substantial hands-on technical contribution and leadership in verification planning, testbench architecture, debug, coverage analysis, regression quality, and verification closure.
- Build and promote modern verification workflows, including AI-assisted techniques that improve verification environment development, automation, debug efficiency, coverage analysis, and execution quality.
- Define verification plans, quality metrics, regression strategy, coverage goals, and emulation readiness plans aligned with project milestones.
- Collaborate closely with architecture, design, system engineering, firmware, and physical design partners to identify risks early, resolve complex issues, and deliver high-quality silicon subsystems.
Qualifications
- B.Sc., M.Sc., or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.
- Proven experience and technical excellence in pre-silicon design verification for complex IPs, subsystems, or SoCs, including subsystem integration, and third-party IP integration.
- Significant hands-on experience with modern DV methodologies, verification planning, testbench development, regressions, coverage analysis, debug, and verification closure.
- Experience as a people manager or technical leader driving verification work across multiple engineers.
Preferred Qualifications -
- Proficiency in SystemVerilog-based verification environments and methodologies such as UVM, assertions, constrained-random verification, and coverage-driven verification, along with Python-based automation and modern verification infrastructure workflows.
- Experience applying AI-assisted techniques to improve silicon design or verification productivity, debug, coverage, automation, or workflow efficiency.
- Hands-on experience with Python, Linux, Git-based development workflows, and automation infrastructure.
- Experience with formal verification, low-power verification, performance verification, or subsystem-level verification.
- Experience with security-oriented silicon subsystems, including crypto engines, memory protection, secure boot, trusted execution, or related hardware security domains.
- Experience with emulation platforms such as Palladium.
- Experience leading or working in teams that include both design and verification engineers.
- Familiarity with physical design considerations, synthesis, constraints, timing closure, or design handoff flows.
- Proven problem-solving, communication, ownership, and cross-team collaboration skills.
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This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
Skills Required
- B.Sc., M.Sc., or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.
- Proven experience in pre-silicon design verification for complex IPs, subsystems, or SoCs, including subsystem integration and third-party IP integration.
- Significant hands-on experience with modern DV methodologies: verification planning, testbench development, regressions, coverage analysis, debug, and verification closure.
- Experience as a people manager or technical leader driving verification work across multiple engineers.
- Proficiency in SystemVerilog-based verification environments and methodologies such as UVM.
- Experience with assertions, constrained-random verification, and coverage-driven verification.
- Python-based automation and modern verification infrastructure workflows.
- Experience applying AI-assisted techniques to improve silicon design or verification productivity, debug, coverage, or automation.
- Hands-on experience with Python, Linux, and Git-based development workflows.
- Experience with formal verification, low-power verification, performance verification, or subsystem-level verification.
- Experience with security-oriented silicon subsystems (crypto engines, memory protection, secure boot, trusted execution, or related hardware security).
- Experience with emulation platforms such as Palladium.
- Experience leading or working in teams that include both design and verification engineers.
- Familiarity with physical design considerations, synthesis, constraints, timing closure, or design handoff flows.
- Proven problem-solving, communication, ownership, and cross-team collaboration skills.
Microsoft Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Microsoft and has not been reviewed or approved by Microsoft.
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Fair & Transparent Compensation — Pay is presented as broadly competitive overall, with clear role/level/location variation and an emphasis on using posted ranges and band information for apples-to-apples comparisons.
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Retirement Support — Retirement benefits are described as a standout, highlighted by a strong 401(k) match structure and immediate vesting, plus additional plan features for tax-advantaged saving.
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Parental & Family Support — Family-oriented benefits are portrayed as a meaningful strength, with substantial paid parental leave and added supports like back-up care and adoption/surrogacy assistance.
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