Physical Design Lead

As a Physical Design Lead Engineer, you will serve as a key technical leader responsible for the end-to-end physical implementation of complex SoCs and IPs on advanced technology nodes. You will own large and challenging design partitions or drive critical top-level physical design activities, including floorplanning, place-and-route, timing closure, and signoff.

You will play a pivotal role in achieving ambitious power, performance, area (PPA), quality, and schedule goals while providing technical leadership, mentoring engineers, and driving methodology improvements across multiple projects.

• Lead and execute all aspects of physical design from RTL to GDSII, including synthesis, floorplanning, power planning, place and route, clock tree synthesis (CTS), timing closure, physical verification, and tapeout.
• Own the complete physical implementation of complex SoC partitions, subsystems, or top-level designs and drive closure to production-quality signoff.
• Perform and drive advanced static timing analysis (STA), multi-corner multi-mode (MCMM) optimization, timing ECO implementation, and signoff closure.
• Drive closure across power, performance, area, signal integrity (SI), electromigration (EM), IR-drop, reliability, and manufacturability targets.
• Develop and optimize physical design methodologies, automation frameworks, flows, and scripts to improve design quality, efficiency, and turnaround time.
• Analyze critical timing paths, congestion, routing, and power bottlenecks, and develop innovative solutions to achieve aggressive PPA goals.
• Collaborate closely with architecture, RTL design, verification, DFT, package, and technology teams to resolve implementation challenges and optimize overall product quality.
• Drive physical signoff activities including DRC, LVS, antenna checks, density closure, metal fill verification, and tapeout readiness reviews.
• Contribute to architecture and design reviews by providing implementation-driven feedback to improve PPA and physical feasibility.
• Evaluate and deploy new EDA tools, methodologies, and advanced implementation techniques.
• Implement advanced low-power design methodologies including clock gating, power gating, multi-voltage design, retention, isolation, and UPF/CPF-based flows.
• Mentor and guide engineers, providing technical leadership and fostering engineering excellence across teams.
• Generate comprehensive implementation reports, signoff documentation, and design reviews throughout the development cycle.

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• 15+ years of ASIC/SoC physical design experience with a proven record of successful tapeouts on advanced process technologies.
• Extensive hands-on experience in synthesis, floorplanning, place and route, timing analysis, physical verification, and signoff closure.
• Proven ability to independently drive block-level, subsystem-level, and top-level implementation of complex multi-million gate SoCs, including multi-processor architectures.
• Strong expertise in one or more of the following domains: Physical Design & Implementation Synthesis & Timing Analysis
• Deep understanding of MCMM timing closure methodologies, timing constraint development, ECO implementation, and signoff flows.
• Hands-on experience with industry-standard EDA tools, including: Cadence Innovus and Tempus Synopsys Fusion Compiler, ICC2, and PrimeTime Ansys RedHawk or equivalent EM/IR analysis tools
• Strong knowledge of physical signoff methodologies including DRC, LVS, antenna checks, density validation, and metal fill closure.
• Experience with signal integrity analysis, crosstalk mitigation, electromigration (EM), and IR-drop closure.
• Strong understanding of manufacturability requirements and Design for Manufacturability (DFM) principles.
• Proficiency in Tcl scripting and working knowledge of Python and/or Perl for automation, reporting, and flow development.
• Demonstrated ability to drive multiple implementation experiments and optimize designs against challenging PPA targets.
• Experience with advanced process nodes including 16nm FinFET and below; experience in 7nm, 5nm, or more advanced technologies is a plus.
• Hands-on experience with low-power design techniques including clock gating, power gating, multi-voltage implementation, retention, isolation, and UPF/CPF methodologies.
• Demonstrated technical leadership, mentorship, and ability to drive cross-functional initiatives.
• Excellent problem-solving, analytical, debugging, communication, and stakeholder management skills.
• Ability to thrive in a fast-paced, collaborative, and globally distributed engineering environment.

• Experience leading physical implementation and signoff for large-scale SoCs across multiple engineering sites.
• Experience developing organization-wide design methodologies, automation frameworks, and best practices.
• Strong understanding of advanced-node challenges including congestion management, variation-aware timing closure, power integrity, and reliability signoff.
• Experience evaluating and deploying next-generation EDA technologies and AI-assisted design optimization techniques.

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