The Role
Own and execute RTL/gate-level netlist-to-GDSII physical implementation for ASIC/SoC blocks: floorplanning, placement and routing, CTS, STA, power integrity, DRC/LVS/IR-drop closure, and sign-off-ready tape-out delivery.
Summary Generated by Built In
ACG_3698_JOB
Our client is a leading technology company in Vietnam who is looking for a qualified candidate to join their firm.
Position Overview
We are looking for a Physical Design Engineer to manage and execute the complete RTL-to-GDSII implementation flow for ASIC and SoC designs. This position covers key physical design activities, including floorplanning, placement and routing, timing closure, power integrity analysis, and physical verification, with the objective of delivering high-quality, tape-out-ready silicon.
Note: This opportunity is available to qualified candidates based anywhere in Vietnam. Remote or hybrid working arrangements may be considered depending on project requirements and the nature of the role.
Key Responsibilities
- Execute the complete RTL or gate-level netlist-to-GDSII implementation flow for individual design blocks or the full chip.
- Take full ownership of the physical implementation of assigned design partitions or blocks.
- Deliver timing-clean blocks that meet all sign-off requirements, including design rule checking (DRC), layout versus schematic (LVS), and IR-drop closure, to ensure tape-out readiness.
- Perform floorplanning and power planning activities.
- Drive timing closure and conduct static timing analysis (STA).
- Implement clock tree synthesis (CTS) and address signal integrity issues.
- Conduct physical verification and complete all required sign-off activities.
Requirements
Education
- Bachelor’s or Master’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related discipline.
Experience
- At least one year of professional experience in Physical Design.
- Hands-on experience with the RTL or gate-level netlist-to-GDSII implementation flow.
- Experience working with advanced process technologies, preferably ranging from 28nm to 3nm.
Technical Expertise
- Strong knowledge of physical design implementation, including floorplanning, placement and routing, clock tree synthesis, timing closure, power integrity, and physical verification.
- Experience with multi-Vt and multi-voltage design methodologies.
- Understanding of low-power design implementation using UPF or CPF.
- Familiarity with DFT-aware physical implementation.
EDA Tools
- Proficiency in place-and-route tools such as Cadence Innovus, Synopsys IC Compiler II, or Fusion Compiler.
- Experience with timing and power analysis tools, including PrimeTime, Tempus, Voltus, or PowerReplay.
- Hands-on knowledge of physical verification tools such as Calibre, Pegasus, or IC Validator.
Programming and Scripting
- Proficiency in Python, Perl, or Shell scripting for workflow automation and process optimization.
Soft Skills
- Strong analytical, problem-solving, and debugging capabilities.
- Effective communication skills with the ability to collaborate across functions and technical teams.
Benefits
- Insurance coverage based on the employee’s full salary, together with a 13th-month salary.
- Full salary entitlement from the first working day, including during the probationary period.
- Comprehensive Bao Viet healthcare insurance for employees and their family members.
- Opportunity to work in a fast-paced, flexible, and multinational environment, with potential onsite assignments across 60 countries.
- Access to internal technical and functional training programs, including English-language training.
- A total of 18 days of paid leave per year, comprising 12 days of annual leave and 6 days of personal leave.
Contact: Thuong Le
Due to the immense number of applications, only shortlisted candidates will be contacted.
Skills Required
- Bachelor's or Master's degree in Electronics, Electrical, Computer Engineering, or related discipline.
- At least one year of professional experience in Physical Design.
- Hands-on experience with RTL or gate-level netlist-to-GDSII implementation flow.
- Experience with advanced process technologies (preferably 28nm to 3nm).
- Knowledge of floorplanning, placement and routing, clock tree synthesis, timing closure, power integrity, and physical verification.
- Experience with multi-Vt and multi-voltage design methodologies.
- Understanding of low-power design implementation using UPF or CPF.
- Familiarity with DFT-aware physical implementation.
- Proficiency in place-and-route tools such as Cadence Innovus, Synopsys IC Compiler II, or Fusion Compiler.
- Experience with timing and power analysis tools including PrimeTime, Tempus, Voltus, or PowerReplay.
- Hands-on knowledge of physical verification tools such as Calibre, Pegasus, or IC Validator.
- Proficiency in Python, Perl, or Shell scripting for automation and process optimization.
- Strong analytical, problem-solving, and debugging capabilities and effective cross-functional communication skills.
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The Company
What We Do
Aloha Consulting Group (ACG) is a consulting firm specializing in digital transformation, technology, marketing, investment, and financial services. Its mission is to make finding rewarding jobs easier and to be a leading firm in Southeast Asia by leveraging human elements and technology.
