We are hiring a Physical Design Engineer to join our VLSI backend team. You will work on floorplanning, placement, and routing for design blocks, contributing to timing and area closure from RTL handoff through tapeout.
Key Responsibilities:
- Floorplanning, power planning, placement, and clock tree synthesis
- Routing, DRC/LVS clean-up, and signoff checks
- Timing closure at block level across corners and modes
- Physical verification and ECO implementation
- Collaborate with STA, DFT, and RTL design teams on block-level closure
- Support full-chip integration activities as needed
Requirements:
- 4-5 years of hands-on experience in physical design (floorplan through signoff)
- Proficiency with industry-standard P&R tools (ICC2/Innovus or equivalent)
- Solid understanding of STA fundamentals and DRC/LVS signoff flows
Skills Required
- 4-5 years of hands-on physical design experience from floorplanning through signoff
- Proficiency with industry-standard place-and-route tools such as ICC2 or Innovus
- Solid understanding of static timing analysis fundamentals
- Experience with DRC/LVS signoff flows
What We Do
nHRMS is a strategic human-resources partner providing end-to-end solutions for organizations in the United States and India. Its services span executive search and talent acquisition, performance management, HR advisory, organization strategy, HR technology, leadership development, labor-code compliance, workforce productivity, and learning. The firm supports clients across the employee lifecycle, combining people-first consulting with technology-enabled systems to help organizations scale.
.jpg)
